attempting to add SPRs to rfid test

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index be71caaae3acd6f48fb1f6a1cdb7870e8c46cf88..e6ee584035d77db781e75a4ddd5b119496f573fb 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -582,6 +582,10 @@ class PowerDecode2(Elaboratable):
         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 
+        # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
+        with m.If(op.internal_op == InternalOp.OP_TRAP):
+            comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
+
         return m
 
         # privileged instruction