Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / experiment / imem.py

diff --git a/src/soc/experiment/imem.py b/src/soc/experiment/imem.py
index 6b51ed77f2952115b0a947f64dac5f09b299cdbc..177e238c781205c813b8deec6173970b16ccce00 100644 (file)
--- a/src/soc/experiment/imem.py
+++ b/src/soc/experiment/imem.py
@@ -7,7 +7,7 @@ from nmigen.cli import rtlil
 class TestMemFetchUnit(FetchUnitInterface, Elaboratable):
 
     def __init__(self, pspec):
-        print ("testmemfetchunit", pspec.addr_wid, pspec.reg_wid)
+        print("testmemfetchunit", pspec.addr_wid, pspec.reg_wid)
         super().__init__(pspec)
         # limit TestMemory to 2^6 entries of regwid size
         self.mem = TestMemory(self.data_wid, 6, readonly=True)
@@ -23,13 +23,13 @@ class TestMemFetchUnit(FetchUnitInterface, Elaboratable):
         m.submodules.mem = mem = self.mem
 
         do_fetch = Signal()  # set when fetch while valid and not stalled
-        m.d.comb += do_fetch.eq(self.a_valid_i & ~self.a_stall_i)
+        m.d.comb += do_fetch.eq(self.a_i_valid & ~self.a_stall_i)
 
         # bit of a messy FSM that progresses from idle to in progress
         # to done.
         op_actioned = Signal(reset=0)
         op_in_progress = Signal(reset=0)
-        with m.If(~op_actioned & do_fetch): # idle
+        with m.If(~op_actioned & do_fetch):  # idle
             m.d.sync += op_actioned.eq(1)
             m.d.sync += op_in_progress.eq(1)
         with m.Elif(op_in_progress):                    # in progress
@@ -37,23 +37,23 @@ class TestMemFetchUnit(FetchUnitInterface, Elaboratable):
         with m.If(~do_fetch):               # done
             m.d.sync += op_in_progress.eq(0)
 
-        m.d.comb += self.a_busy_o.eq(op_actioned & self.a_valid_i)
+        m.d.comb += self.a_busy_o.eq(op_actioned & self.a_i_valid)
         # fetch
         m.d.comb += mem.rdport.addr.eq(self.a_pc_i[adr_lsb:])
         m.d.comb += self.f_instr_o.eq(mem.rdport.data)
 
         return m
 
-    def __iter__(self): # TODO
+    def __iter__(self):  # TODO
         yield self.a_pc_i
         yield self.f_instr_o
 
     def ports(self):
         return list(self)
 
+
 if __name__ == '__main__':
     dut = TestMemFetchUnit(addr_wid=32, data_wid=32)
-    vl = rtlil.convert(dut, ports=[]) # TODOdut.ports())
+    vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
     with open("test_imem.il", "w") as f:
         f.write(vl)
-