+ def op_sim_fsm(a, b, direction, expected, delays):
+ print("op_sim_fsm", a, b, direction, expected)
+ yield dut.issue_i.eq(0)
+ yield
+ # forward data and delays to the producers and consumers
+ yield from producers[0].send(a, delays[0])
+ yield from producers[1].send(b, delays[1])
+ yield from consumers[0].receive(expected, delays[2])
+ # submit operation, and assert issue_i for one cycle
+ yield dut.oper_i.sdir.eq(direction)
+ yield dut.issue_i.eq(1)
+ yield
+ yield dut.issue_i.eq(0)
+ # wait for busy to be negated
+ yield Settle()
+ while (yield dut.busy_o):
+ yield
+ yield Settle()
+ # update the operation count
+ nonlocal op_count
+ op_count = (op_count + 1) & 255
+ # check that producers and consumers have the same count
+ # this assures that no data was left unused or was lost
+ assert (yield producers[0].count) == op_count
+ assert (yield producers[1].count) == op_count
+ assert (yield consumers[0].count) == op_count
+
+ # 13 >> 2 = 3
+ # operand 1 arrives immediately
+ # operand 2 arrives after operand 1
+ # write data is accepted immediately
+ yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
+ # 3 << 4 = 48
+ # operand 2 arrives immediately
+ # operand 1 arrives after operand 2
+ # write data is accepted after some delay
+ yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
+ # 21 << 0 = 21
+ # operands 1 and 2 arrive at the same time
+ # write data is accepted after some delay
+ yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
+
+
+def scoreboard_sim_dummy(op):
+ yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
+ src_delays=[0, 2, 1], dest_delays=[0])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ # test all combinations of masked input ports
+ yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 0, 0],
+ src_delays=[0, 2, 1], dest_delays=[0])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
+ rdmaskn=[0, 1, 0],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
+ rdmaskn=[0, 0, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
+ rdmaskn=[0, 1, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 1, 0],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 1, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])
+
+
+class OpSim:
+ """ALU Operation issuer
+
+ Issues operations to the DUT"""
+ def __init__(self, dut, sim):
+ self.op_count = 0
+ self.zero_a_count = 0
+ self.imm_ok_count = 0
+ self.rdmaskn_count = [0] * len(dut.src_i)
+ self.dut = dut
+ # create one operand producer for each input port
+ self.producers = list()
+ for i in range(len(dut.src_i)):
+ self.producers.append(OperandProducer(sim, dut, i))
+ # create one result consumer for each output port
+ self.consumers = list()
+ for i in range(len(dut.dest)):
+ self.consumers.append(ResultConsumer(sim, dut, i))
+ def issue(self, src_i, op, expected, src_delays, dest_delays,
+ inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=None):
+ """Executes the issue operation"""
+ dut = self.dut
+ producers = self.producers
+ consumers = self.consumers
+ if rdmaskn is None:
+ rdmaskn = [0] * len(src_i)
+ yield dut.issue_i.eq(0)
+ yield
+ # forward data and delays to the producers and consumers
+ # first, send special cases (with zero_a and/or imm_ok)
+ if not zero_a:
+ yield from producers[0].send(src_i[0], src_delays[0])
+ if not imm_ok:
+ yield from producers[1].send(src_i[1], src_delays[1])
+ # then, send the rest (if any)
+ for i in range(2, len(producers)):
+ yield from producers[i].send(src_i[i], src_delays[i])
+ for i in range(len(consumers)):
+ yield from consumers[i].receive(expected[i], dest_delays[i])
+ # submit operation, and assert issue_i for one cycle
+ yield dut.oper_i.insn_type.eq(op)
+ if hasattr(dut.oper_i, "invert_in"):
+ yield dut.oper_i.invert_in.eq(inv_a)
+ if hasattr(dut.oper_i, "imm_data"):
+ yield dut.oper_i.imm_data.data.eq(imm)
+ yield dut.oper_i.imm_data.ok.eq(imm_ok)
+ if hasattr(dut.oper_i, "zero_a"):
+ yield dut.oper_i.zero_a.eq(zero_a)
+ if hasattr(dut, "rdmaskn"):
+ rdmaskn_bits = 0
+ for i in range(len(rdmaskn)):
+ rdmaskn_bits |= rdmaskn[i] << i
+ yield dut.rdmaskn.eq(rdmaskn_bits)
+ yield dut.issue_i.eq(1)
+ yield
+ yield dut.issue_i.eq(0)
+ # deactivate decoder inputs along with issue_i, so we can be sure they
+ # were latched at the correct cycle
+ # note: rdmaskn is not latched, and must be held as long as
+ # busy_o is active
+ # todo: is the above restriction on rdmaskn intentional?
+ # todo: shouldn't it be latched by issue_i, like the others?
+ yield self.dut.oper_i.insn_type.eq(0)
+ if hasattr(dut.oper_i, "invert_in"):
+ yield self.dut.oper_i.invert_in.eq(0)
+ if hasattr(dut.oper_i, "imm_data"):
+ yield self.dut.oper_i.imm_data.data.eq(0)
+ yield self.dut.oper_i.imm_data.ok.eq(0)
+ if hasattr(dut.oper_i, "zero_a"):
+ yield self.dut.oper_i.zero_a.eq(0)
+ # wait for busy to be negated
+ yield Settle()
+ while (yield dut.busy_o):
+ yield
+ yield Settle()
+ # now, deactivate rdmaskn
+ if hasattr(dut, "rdmaskn"):
+ yield dut.rdmaskn.eq(0)
+ # update the operation count
+ self.op_count = (self.op_count + 1) & 255
+ # On zero_a, imm_ok and rdmaskn executions, the producer counters will
+ # fall behind. But, by summing the following counts, the invariant is
+ # preserved.
+ if zero_a and not rdmaskn[0]:
+ self.zero_a_count = self.zero_a_count + 1
+ if imm_ok and not rdmaskn[1]:
+ self.imm_ok_count = self.imm_ok_count + 1
+ for i in range(len(rdmaskn)):
+ if rdmaskn[i]:
+ self.rdmaskn_count[i] = self.rdmaskn_count[i] + 1
+ # check that producers and consumers have the same count
+ # this assures that no data was left unused or was lost
+ # first, check special cases (zero_a and imm_ok)
+ port_a_cnt = \
+ (yield producers[0].count) \
+ + self.zero_a_count \
+ + self.rdmaskn_count[0]
+ port_b_cnt = \
+ (yield producers[1].count) \
+ + self.imm_ok_count \
+ + self.rdmaskn_count[1]
+ assert port_a_cnt == self.op_count
+ assert port_b_cnt == self.op_count
+ # then, check the rest (if any)
+ for i in range(2, len(producers)):
+ port_cnt = (yield producers[i].count) + self.rdmaskn_count[i]
+ assert port_cnt == self.op_count
+ # check write counter
+ for i in range(len(consumers)):
+ assert (yield consumers[i].count) == self.op_count
+
+
+def scoreboard_sim(op):