Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / common_output_stage.py

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 23e83f57ee4ebe5aa4a1cb26d392882bfe0ccce1..a79179bc3503e60585d0b0748ad7719da36e26f6 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -2,7 +2,7 @@
 # and updating the condition register
 from nmigen import (Module, Signal, Cat, Const)
 from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 
@@ -11,6 +11,7 @@ class CommonOutputStage(PipeModBase):
         super().__init__(pspec, "output")
 
     def elaborate(self, platform):
+        XLEN = self.pspec.XLEN
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
@@ -34,20 +35,22 @@ class CommonOutputStage(PipeModBase):
         else:
             so = xer_so_i
 
-        # op requests inversion of the output...
-        o = Signal.like(self.i.o)
-        if hasattr(op, "invert_out"): # ... optionally
-            with m.If(op.invert_out):
-                comb += o.eq(~self.i.o.data)
-            with m.Else():
-                comb += o.eq(self.i.o.data)
-        else:
-            comb += o.eq(self.i.o.data) # ... no inversion
+        with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
+            # op requests inversion of the output...
+            o = Signal.like(self.i.o)
+            if hasattr(op, "invert_out"): # ... optionally
+                with m.If(op.invert_out):
+                    comb += o.eq(~self.i.o.data)
+                with m.Else():
+                    comb += o.eq(self.i.o.data)
+            else:
+                comb += o.eq(self.i.o.data) # ... no inversion
 
         # target register if 32-bit is only the 32 LSBs
         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
+        # (an MSR bit)
         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
-        target = Signal(64, reset_less=True)
+        target = Signal(XLEN, reset_less=True)
         #with m.If(op.is_32bit):
         #    comb += target.eq(o[:32])
         #with m.Else():
@@ -77,7 +80,7 @@ class CommonOutputStage(PipeModBase):
         comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
         comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
 
-        comb += msb_test.eq(target[-1]) # 64-bit MSB
+        comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
         comb += is_nzero.eq(target.bool())
         comb += is_negative.eq(msb_test)
         comb += is_positive.eq(is_nzero & ~msb_test)
@@ -87,15 +90,11 @@ class CommonOutputStage(PipeModBase):
         with m.Else():
             comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
 
-        with m.If(~op.sv_pred_dz):
-            # copy out [inverted?] output, cr0, and context out
-            comb += self.o.o.data.eq(o)
-            comb += self.o.cr0.data.eq(cr0) # CR0 to be set
-
-        # set output to write
+        # copy out [inverted?] output, cr0, and context out
+        comb += self.o.o.data.eq(o)
         comb += self.o.o.ok.eq(self.i.o.ok)
+        comb += self.o.cr0.data.eq(cr0) # CR0 to be set
         comb += self.o.cr0.ok.eq(op.write_cr0)
-        # context
-        comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.ctx.eq(self.i.ctx) # context
 
         return m