rename regspecs to give a consistent naming scheme

[soc.git] / src / soc / fu / compunits / test / test_alu_compunit.py

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 0c7b0623b4b02ea742627f7ce950a3751260f95c..124752501b21db14d1f9879c09bbaa26a39d357d 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -23,13 +23,13 @@ class ALUTestRunner(TestRunner):
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data

-            res['a'] = sim.gpr(data1).value
+            res['ra'] = sim.gpr(data1).value

 
         # RB (or immediate)
         reg2_ok = yield dec2.e.read_reg2.ok
         if reg2_ok:
             data2 = yield dec2.e.read_reg2.data
 
         # RB (or immediate)
         reg2_ok = yield dec2.e.read_reg2.ok
         if reg2_ok:
             data2 = yield dec2.e.read_reg2.data

-            res['b'] = sim.gpr(data2).value
+            res['rb'] = sim.gpr(data2).value

 
         # XER.ca
         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 
         # XER.ca
         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0


@@ -69,7 +69,7 @@ class ALUTestRunner(TestRunner):
         # CR (CR0-7)
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value
         # CR (CR0-7)
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value

-            cr_actual = res['cr0']
+            cr_actual = res['cr_a']

             print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 
             print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))