Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index e59a81ebe2b00af390ede2c4c04674856dbfa61c..f1c6d349201915764682ae5079cc1753f9c94b10 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,64 +1,34 @@
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
-from soc.decoder.power_decoder2 import Data
+"""
+Links:
+* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
+"""
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
+from soc.fu.cr.cr_input_record import CompCROpSubset
 
 
-class CRInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),      # 64 bit range
+class CRInputData(FUBaseData):
+    regspec = [('INT', 'ra', '0:63'),      # 64 bit range
+               ('INT', 'rb', '0:63'),      # 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
-               ('CR', 'cr_c', '0:3')]     # 4 bit range
+               ('CR', 'cr_c', '0:3')]     # 4 bit: for CR_OP partial update
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.full_cr = Signal(32, reset_less=True) # full CR in
-        self.cr_a = Signal(4, reset_less=True)
-        self.cr_b = Signal(4, reset_less=True)
-        self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.a
-        yield self.full_cr
-        yield self.cr_a
-        yield self.cr_b
-        yield self.cr_c
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.a.eq(i.a),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_a.eq(i.cr_a),
-                      self.cr_b.eq(i.cr_b),
-                      self.cr_c.eq(i.cr_c)]
-                      
-
-class CROutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),      # 64 bit range
+class CROutputData(FUBaseData):
+    regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
-               ('CR', 'cr_o', '0:3')]     # 4 bit range
+               ('CR', 'cr_a', '0:3')]     # 4 bit range
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Signal(64, reset_less=True) # RA
-        self.full_cr = Data(32, name="cr_out") # CR in
-        self.cr_o = Data(4, name="cr_o")
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.full_cr
-        yield self.cr_o
+        super().__init__(pspec, True)
+        # convenience
+        self.cr = self.cr_a
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_o.eq(i.cr_o)]
 
-# TODO: replace CompALUOpSubset with CompCROpSubset
 class CRPipeSpec(CommonPipeSpec):
-    regspec = (CRInputData.regspec, CROutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+    regspecklses = (CRInputData, CROutputData)
+    opsubsetkls = CompCROpSubset