Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / div / core_stages.py

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index 3bbde7dba509721545a51a6d223974091db3fc28..e271876b26e41b1f74a6bd919dd985691cae00b0 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,14 +3,14 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.logical.pipe_data import LogicalInputData
-from soc.fu.alu.pipe_data import ALUOutputData
-from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
-
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
-from soc.fu.div.pipe_data import CoreInputData, CoreInterstageData, CoreOutputData
+from ieee754.part.partsig import SimdSignal
+from openpower.decoder.power_enums import MicrOp
+
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
+from soc.fu.div.pipe_data import (CoreInputData,
+                                  CoreInterstageData,
+                                  CoreOutputData)
 from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage)
@@ -27,10 +27,12 @@ class DivCoreBaseStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()
 
+        # pass-through on non-core parameters
         m.d.comb += self.o.eq_without_core(self.i)
 
         m.submodules.core = self.core
 
+        # copy parameters to/from divremsqrt core into the Base, here.
         m.d.comb += self.core.i.eq(self.i.core)
         m.d.comb += self.o.core.eq(self.core.o)
 
@@ -39,7 +41,8 @@ class DivCoreBaseStage(PipeModBase):
 
 class DivCoreSetupStage(DivCoreBaseStage):
     def __init__(self, pspec):
-        super().__init__(pspec, "core_setup_stage", DivPipeCoreSetupStage)
+        super().__init__(pspec, "core_setup_stage",
+                         pspec.div_pipe_kind.config.core_setup_stage_class)
 
     def ispec(self):
         return CoreInputData(self.pspec)
@@ -50,8 +53,9 @@ class DivCoreSetupStage(DivCoreBaseStage):
 
 class DivCoreCalculateStage(DivCoreBaseStage):
     def __init__(self, pspec, stage_index):
+        stage = pspec.div_pipe_kind.config.core_calculate_stage_class
         super().__init__(pspec, f"core_calculate_stage_{stage_index}",
-                         DivPipeCoreCalculateStage, stage_index)
+                         stage, stage_index)
 
     def ispec(self):
         return CoreInterstageData(self.pspec)
@@ -62,7 +66,8 @@ class DivCoreCalculateStage(DivCoreBaseStage):
 
 class DivCoreFinalStage(DivCoreBaseStage):
     def __init__(self, pspec):
-        super().__init__(pspec, "core_final_stage", DivPipeCoreFinalStage)
+        super().__init__(pspec, "core_final_stage",
+                         pspec.div_pipe_kind.config.core_final_stage_class)
 
     def ispec(self):
         return CoreInterstageData(self.pspec)