Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / div / core_stages.py

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index fc1d7520e0b094a0b8c32da2d026bd65c9a7cb15..e271876b26e41b1f74a6bd919dd985691cae00b0 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,11 +3,11 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from ieee754.part.partsig import SimdSignal
+from openpower.decoder.power_enums import MicrOp
 
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
 from soc.fu.div.pipe_data import (CoreInputData,
                                   CoreInterstageData,
                                   CoreOutputData)