dcbz and tlbie first test, still incomplete

[soc.git] / src / soc / fu / mmu / test / test_pipe_caller.py

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index 2290597f6ce5c525b6f847371f97cea68ca43b90..373cd658becd4a9cb41876203686b11536b7f7dc 100644 (file)
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -85,8 +85,8 @@ class MMUTestCase(TestAccumulatorBase):
                #"mfspr 27, 4", # SRR1
 
                #next two need to be added to the simulator
-               #"dcbz 5,6" # Data Cache Block set to Zero - RA,RB
-               #"tlbie 1,1,1,1,1"
+               #"dcbz 5,6" # Data Cache Block set to Zero - RA,RB (hangs)
+               "tlbie 1,1,1,1,1" #does not hang -- not verified yet
                ]
 
         initial_regs = [0] * 32