attempting to add SPRs to rfid test

[soc.git] / src / soc / fu / trap / test / test_pipe_caller.py

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 4f1af455227285e53ff02f0f2e56a3b0b83cc3c4..1d3c7f8dc940847c486fa21a53bbbdf049125ce7 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -82,7 +82,8 @@ class TrapTestCase(FHDLTestCase):
         lst = ["rfid"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
         lst = ["rfid"]
         initial_regs = [0] * 32
         initial_regs[1] = 1

-        self.run_tst_program(Program(lst), initial_regs)
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+        self.run_tst_program(Program(lst), initial_regs, initial_sprs)

 
     def test_0_trap_eq_imm(self):
         insns = ["tw", "td"]
 
     def test_0_trap_eq_imm(self):
         insns = ["tw", "td"]