core_sync = ClockDomain("coresync")
m.domains += cd_por, cd_sync, core_sync
core_sync = ClockDomain("coresync")
m.domains += cd_por, cd_sync, core_sync
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
comb += core_sync.clk.eq(ClockSignal())
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
comb += core_sync.clk.eq(ClockSignal())
# instruction allowed to go: start by reading the PC
# capture the PC and also drop it into Insn Memory
# we have joined a pair of combinatorial memory
# instruction allowed to go: start by reading the PC
# capture the PC and also drop it into Insn Memory
# we have joined a pair of combinatorial memory
comb += pll.clk_24_i.eq(clksel.clk_24_i)
# now wire up ResetSignals. don't mind them all being in this domain
comb += pll.clk_24_i.eq(clksel.clk_24_i)
# now wire up ResetSignals. don't mind them all being in this domain
- comb += pll.rst.eq(ResetSignal())
- comb += clksel.rst.eq(ResetSignal())
+ int_rst = ResetSignal("intclk")
+ pll_rst = ResetSignal("pllclk")
+ comb += int_rst.eq(ResetSignal())
+ comb += pll_rst.eq(ResetSignal())