Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / decoder / isa / test_caller_svp64_predication.py
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-04-21 Cesar StraussFix comment in CR predication test case
2021-04-10 Cesar StraussAdd test cases for 1<<r3 predication
2021-04-06 Cesar StraussStart the test case from a point where the predicate...
2021-04-04 Cesar StraussAdd test case for reentrant VL loop
2021-04-03 Cesar StraussAdd twin predication test
2021-04-02 Cesar StraussAdd VEXPAND test case for the ISA Simulator
2021-04-02 Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
2021-04-02 Cesar StraussDisallow dm=xx on single predication
2021-03-22 Luke Kenneth Casso... read predicate mask from correct point in SVP64Asm
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-20 Luke Kenneth Casso... sort out predicate zeroing in ISACaller
2021-03-20 Luke Kenneth Casso... attempting to add src/dest-zeroing to ISACaller
2021-03-17 Luke Kenneth Casso... correct comments
2021-03-17 Luke Kenneth Casso... re-enable SVP64 ISACaller predicate tests
2021-03-17 Luke Kenneth Casso... add ascii graphic for extsw svp64 operation
2021-03-17 Luke Kenneth Casso... add more explanatory comments
2021-03-17 Luke Kenneth Casso... add twin-predicated extsw SVP64 ISACaller unit test
2021-03-17 Luke Kenneth Casso... add CR-based predication to ISACaller
2021-03-17 Luke Kenneth Casso... add predication SVP64 unit test