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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
decoder
/
isa
/ test_caller_svp64_predication.py
2021-04-23
Luke Kenneth Casso...
removing more as moved over to openpower-isa
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2021-04-21
Cesar Strauss
Fix comment in CR predication test case
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2021-04-10
Cesar Strauss
Add test cases for 1<<r3 predication
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2021-04-06
Cesar Strauss
Start the test case from a point where the predicate...
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2021-04-04
Cesar Strauss
Add test case for reentrant VL loop
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2021-04-03
Cesar Strauss
Add twin predication test
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2021-04-02
Cesar Strauss
Add VEXPAND test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Add VCOMPRESS test case for the ISA Simulator
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2021-04-02
Cesar Strauss
Disallow dm=xx on single predication
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2021-03-22
Luke Kenneth Casso...
read predicate mask from correct point in SVP64Asm
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2021-03-21
Luke Kenneth Casso...
naah. back to "sv." syntax for SVP64 assembly
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2021-03-20
Luke Kenneth Casso...
sort out predicate zeroing in ISACaller
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2021-03-20
Luke Kenneth Casso...
attempting to add src/dest-zeroing to ISACaller
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2021-03-17
Luke Kenneth Casso...
correct comments
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2021-03-17
Luke Kenneth Casso...
re-enable SVP64 ISACaller predicate tests
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2021-03-17
Luke Kenneth Casso...
add ascii graphic for extsw svp64 operation
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2021-03-17
Luke Kenneth Casso...
add more explanatory comments
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2021-03-17
Luke Kenneth Casso...
add twin-predicated extsw SVP64 ISACaller unit test
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2021-03-17
Luke Kenneth Casso...
add CR-based predication to ISACaller
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2021-03-17
Luke Kenneth Casso...
add predication SVP64 unit test
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