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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / experiment / test / test_l0_cache_buffer2.py
2022-02-23 Luke Kenneth Casso... forgot to pass cix (cache-inhibited) through to LD... commit | commitdiff
2021-12-13 Tobias Platenreplace msr_pr with msr commit | commitdiff
2021-10-08 Tobias Platenan extra dcbz parameter in all six places commit | commitdiff
2021-10-03 Tobias Platenan extra dcbz parameter in all six places commit | commitdiff
2021-08-01 Jonathan NeuschäferRename test_dcache, which can't be invoked by test... commit | commitdiff
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1 commit | commitdiff
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase commit | commitdiff
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup commit | commitdiff
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff
2020-08-21 Tobias Platentypo fix in test_l0_cache_buffer2.py commit | commitdiff
2020-08-21 Tobias Platenconnect TestCachedMemoryPortInterface to LDSTSplitter commit | commitdiff
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface commit | commitdiff
2020-08-20 Tobias Platentestcase refactoring commit | commitdiff
2020-08-18 Tobias Platenadd testcase for LDSTSplitter using PortInterface commit | commitdiff
2020-08-11 Tobias Plateninitial version of L0CacheBuffer2 commit | commitdiff