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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
div
/
pipeline.py
2022-05-01
Luke Kenneth Casso...
split out front of div into separate stage, still too...
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2022-04-30
Luke Kenneth Casso...
add missing module
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2022-04-30
Luke Kenneth Casso...
split off CR0/XER production in DIV Function Unit into...
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2020-07-22
Jacob Lifshay
working on fsm
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2020-07-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-18
Jacob Lifshay
add div fsm core (`DivState*`) with tests
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2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-17
Jacob Lifshay
start adding FSMDivCore*
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2020-07-17
Jacob Lifshay
rename DIV->Div to be consistent
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2020-07-17
Jacob Lifshay
format div code
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2020-07-10
Luke Kenneth Casso...
add debugging chain for #425
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2020-07-09
Luke Kenneth Casso...
remove xer_ca from DIV pipeline (took a bit of messing...
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
reduce steps per stage to 8
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2020-07-02
Luke Kenneth Casso...
increase combinatorial stages to 8
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2020-06-29
Luke Kenneth Casso...
sort out syntax errors in div
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2020-06-19
Luke Kenneth Casso...
whitespace update
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2020-06-18
Jacob Lifshay
div pipe completed except for tests
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2020-05-22
Luke Kenneth Casso...
cookie-cut start on div pipe
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