too much debug info going past, so add the test registers to the
[soc.git] / src / soc / fu / div /
2020-07-24 Luke Kenneth Casso... too much debug info going past, so add the test registe...
2020-07-24 Luke Kenneth Casso... missed import
2020-07-24 Luke Kenneth Casso... calling the test dictionary from the constructor is...
2020-07-24 Luke Kenneth Casso... whoops spelling
2020-07-24 Luke Kenneth Casso... add the div pipe kind plus prog.assembly to the assert...
2020-07-24 Luke Kenneth Casso... call test_write_ilang only once - ends up being called...
2020-07-24 Luke Kenneth Casso... fix how long div tests run, de-comment FSM and DivPipeCore
2020-07-24 Luke Kenneth Casso... argh! work-in-progress breaking / fixing how to do...
2020-07-24 Luke Kenneth Casso... whoops must add DivTestCasesLong to get it to produce...
2020-07-24 Luke Kenneth Casso... re-enable commented-out div unit tests
2020-07-24 Luke Kenneth Casso... split out "all" div into separate unit test (takes...
2020-07-24 Luke Kenneth Casso... reduce variable size, continuation not needed
2020-07-24 Luke Kenneth Casso... comment about timeline does not exist
2020-07-24 Luke Kenneth Casso... ah ha! not using "with" was not calling the "close...
2020-07-24 Luke Kenneth Casso... whitespace / comments
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller"
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller
2020-07-23 Jacob Lifshayadd all div* and mod* instructions to test_pipe_caller
2020-07-22 Jacob Lifshayworking on fsm
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage
2020-07-22 Jacob Lifshayfix test_div_state_fsm
2020-07-19 Luke Kenneth Casso... if nmigen.sim.pysim import fails use nmigen.back.pysim
2020-07-18 Luke Kenneth Casso... worked out that DivPipeSpec can be given a default...
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Jacob Lifshaystart adding FSMDivCore*
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Jacob Lifshayadd simulation-only division core using nmigen div...
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-10 Luke Kenneth Casso... add a DIVS function as separate and discrete from floor_div
2020-07-10 Luke Kenneth Casso... add random unsigned div tests
2020-07-10 Luke Kenneth Casso... add overflow div tests
2020-07-10 Luke Kenneth Casso... propagate missing parameters from div
2020-07-10 Luke Kenneth Casso... code comments
2020-07-10 Luke Kenneth Casso... do not set div result if overflow occurs
2020-07-10 Luke Kenneth Casso... re-enable div random tests and other regressions
2020-07-10 Luke Kenneth Casso... add test7 div regression
2020-07-10 Luke Kenneth Casso... add more debug output for #425
2020-07-10 Luke Kenneth Casso... add debugging chain for #425
2020-07-09 Luke Kenneth Casso... add regression test for div overflow case
2020-07-09 Luke Kenneth Casso... test top bit 31 in 32-bit mode for CR0 creation
2020-07-09 Luke Kenneth Casso... ha ha very funny. pipelines being pipelines, you have...
2020-07-09 Luke Kenneth Casso... set xer_ov.ok = 1
2020-07-09 Luke Kenneth Casso... something weird going on with div. interaction between...
2020-07-09 Luke Kenneth Casso... DIV overflow needs to be copied into both bits of XER.ov
2020-07-09 Luke Kenneth Casso... add debug output of DIV results
2020-07-09 Luke Kenneth Casso... check result first then CR second
2020-07-09 Luke Kenneth Casso... resolving issues with div tests (turned out to be nmuti...
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-09 Luke Kenneth Casso... add new stages etc. to get multiply working without...
2020-07-09 Luke Kenneth Casso... create new DivMulOutputData which does not have CA...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... first cut at mul test pipeline
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-04 Luke Kenneth Casso... reduce steps per stage to 8
2020-07-03 Luke Kenneth Casso... set only div/rem supported
2020-07-02 Luke Kenneth Casso... increase combinatorial stages to 8
2020-07-02 Luke Kenneth Casso... reduce DIV radix to 1
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... use correct ALUHelpers in div test
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-29 Luke Kenneth Casso... first unit test for div
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... ilang file output change from alu_pipeline.il to div_pi...
2020-06-10 Luke Kenneth Casso... cookie-cut alu test_pipe_caller.py over
2020-06-10 Jacob Lifshaycreate div pipe setup stage
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-05-23 Luke Kenneth Casso... add gitignore
2020-05-22 Luke Kenneth Casso... div probably uses ALU not Logical, needs double-checkin...
2020-05-22 Luke Kenneth Casso... rename Logical to Div in fu div test
2020-05-22 Luke Kenneth Casso... cookie-cut start on div pipe