capture CR 3 and 5 bit sv encodings
[soc.git] / src / soc / fu /
2021-01-19 Tobias Platentest_issuer_mmu_data_path.py: test both ld and st instr...
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-17 Tobias Platencleanup test_issuer_mmu_data_path.py
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-16 Tobias Platenadd new unittest: test_issuer_mmu_data_path.py
2021-01-15 Tobias Platencleanup test_non_production_core.py
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits
2021-01-15 Tobias Platentest_non_production_core.py: fix hanging test
2021-01-15 Tobias Platentest_non_production_core.py: wire instruction decoder...
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog
2021-01-07 Tobias Platenmfspr is RT, SPR
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr
2021-01-04 Tobias Platentest_countzero.py: rename output files
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-12-12 Luke Kenneth Casso... skip madd, not implemented
2020-12-06 Cesar StraussWhitespace
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof...
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o
2020-11-17 Tobias Platentestcase for dcbz
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete
2020-11-11 Tobias Platenfu/mmu/test/test_pipe_caller.py test case for mfspr
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi...
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz'
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction...
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-16 Luke Kenneth Casso... experiment swapping dummy trap stage over to input
2020-10-16 Luke Kenneth Casso... add extra (test dummy stage in trap to see if combinato...
2020-10-16 Luke Kenneth Casso... add LGPLv3+ notice and add copyright holders
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-09 Jacob Lifshayfinish converting mul tests to use common code
2020-10-09 Jacob Lifshayworking on splitting out common mul pipe test code
2020-10-09 Jacob Lifshayadd carry handling to pia_res_to_output
2020-10-09 Jacob Lifshaymove pia_res_to_output to common test helpers
2020-10-09 Jacob Lifshaymove mul pipe ilang test to separate file
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore...
2020-10-07 Luke Kenneth Casso... missing invert_in field from shiftrot input record
2020-10-07 Jacob Lifshayfix div tests
2020-10-07 Jacob LifshayFix forgotten test_pipe_caller changes from e0b4334c7d8...
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2
2020-10-06 Jacob Lifshayadd divde regression test
2020-10-06 Jacob Lifshayadd moduw regression test
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502
2020-10-06 Jacob Lifshayadd modsw regression
2020-10-06 Jacob Lifshayadd test case for divweu regression
2020-10-06 Jacob Lifshayprint regs in hex
2020-10-04 Jacob Lifshaychange div FSM pipeline unit to not have a combinatoria...
2020-10-03 Jacob Lifshayadd regression testcase
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-26 Luke Kenneth Casso... do not use simdec2 in test_pipe_caller
2020-09-26 Luke Kenneth Casso... fix annoying alu test_pipe_caller bug, missing asmcode
2020-09-26 Luke Kenneth Casso... add alternative PowerDecode2 to branch test_pipe_caller
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-22 Jacob LifshayRevert "disable pia in div tests"
2020-09-22 Luke Kenneth Casso... disable pia in div tests
2020-09-22 Luke Kenneth Casso... add MMU (commented out)
2020-09-21 Luke Kenneth Casso... add missing file
2020-09-18 Luke Kenneth Casso... can remove unneeded overrides of Prev/Next Control
2020-09-17 Jacob Lifshayadd divwe regression test case
2020-09-17 Jacob Lifshayre-enable test case -- no longer goes into an infinite...
2020-09-17 Jacob Lifshayfix bug #492
2020-09-17 Jacob Lifshayreplace sim._state.timeline.now with sim._engine.now
2020-09-15 Luke Kenneth Casso... add back (totally confusing) accidentally-removed code...
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth Casso... do not need FAST regs in MMU
2020-09-15 Luke Kenneth Casso... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth Casso... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth Casso... use convenience vars
2020-09-15 Luke Kenneth Casso... add OP_TLBIE to mmu fsm
2020-09-15 Luke Kenneth Casso... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
2020-09-15 Luke Kenneth Casso... add MMU MTSPR connection into FSM
2020-09-15 Luke Kenneth Casso... add in MMU and DCache into MMU FSM
2020-09-15 Luke Kenneth Casso... add mmu fsm
2020-09-15 Luke Kenneth Casso... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth Casso... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth Casso... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth Casso... removed (confusing/spurious) types, should be in .pyi...
2020-09-15 Luke Kenneth Casso... mmu uses RB, go with it
2020-09-15 Luke Kenneth Casso... add mmu initial pipe_data.py
2020-09-07 Luke Kenneth Casso... create eq_from function based on eq_from_execute1
2020-09-07 Luke Kenneth Casso... debug print statement in eq_from_execute
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