add wishbone driver for test_compldst_multi_mmu.py
[soc.git] / src /
2021-10-04 Tobias Platenadd wishbone driver for test_compldst_multi_mmu.py
2021-10-03 Tobias Platenupdate test_compldst_multi_mmu.py
2021-10-03 Tobias Platensrc/soc/experiment/compldst_multi.py: update signal...
2021-10-03 Tobias Platenuse LoadStore1 and DCache in test_compldst_multi_mmu.py
2021-10-03 Tobias Platenmore cleanup on pimem.py
2021-10-03 Tobias Platenwhitespace
2021-10-03 Tobias Platenremove redunant pi_dcbz
2021-10-03 Tobias Platenan extra dcbz parameter in all six places
2021-10-02 Luke Kenneth Casso... have to remove dcbz from pimem.py entirely
2021-10-02 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-02 Tobias Platendcbz: cleanup
2021-10-02 Tobias Platendcbz symbol rename
2021-10-02 Tobias Platenloadstore.py: add function set_dcbz_addr
2021-10-02 Tobias Platenupdate test_dcbz_pi.py test case
2021-10-02 Tobias PlatenPortInterfaceBase: add dcbz handling
2021-10-01 Luke Kenneth Casso... move TestRunner to openpower-isa now that it is part...
2021-09-29 Tobias Platencompldst_multi.py: pass dcbz to portinterface
2021-09-29 Tobias Platentestcase for compldst: wait for address
2021-09-28 Tobias Platenrename ra_needed to zero_a
2021-09-28 Tobias Platenupdate testcase for dcbz
2021-09-28 Tobias Platenadd testcase for dcbz
2021-09-26 klehmanadd a state list for method calling
2021-09-25 Luke Kenneth Casso... found accidental commenting-out of memory setup in...
2021-09-25 Luke Kenneth Casso... move debug printout to see whats going on for ldst
2021-09-25 Luke Kenneth Casso... comments
2021-09-25 Luke Kenneth Casso... Revert "move coresync clock synchronisation into HDLRunner"
2021-09-25 Luke Kenneth Casso... call StateRunner constructor, to add to StateRunner...
2021-09-25 Luke Kenneth Casso... more TODO comments
2021-09-25 Luke Kenneth Casso... move coresync clock synchronisation into HDLRunner
2021-09-25 Luke Kenneth Casso... whoops missed one function which should be a yield...
2021-09-25 Luke Kenneth Casso... use yield from on StateRunners
2021-09-25 Luke Kenneth Casso... add comments, remove unneeded code
2021-09-25 Luke Kenneth Casso... move pc_i and svstate_i to HDLRunner
2021-09-25 klehmanadd end_test, minor cleanup, added hdlrun.cleanup(...
2021-09-25 klehmanmoved pc_i and sv_state to constructor, remove hdl_stat...
2021-09-25 klehmanchange over run_hdl_state to TestRunner class
2021-09-25 Luke Kenneth Casso... add dummy call to simrun and end_test()
2021-09-25 Luke Kenneth Casso... code-comments and dummy functions
2021-09-25 Luke Kenneth Casso... move contents of run_sim_state into SimRunner run_test...
2021-09-25 Luke Kenneth Casso... add a SimRunner prepare_for_test and run_test function
2021-09-25 klehmanstart of HDLRunner
2021-09-24 Luke Kenneth Casso... create initial SimRunner
2021-09-24 Luke Kenneth Casso... add shiftrot2 tests to test_issuer.py
2021-09-23 Luke Kenneth Casso... move pc_i and svstate_i inside if self.run_hdl
2021-09-23 Luke Kenneth Casso... more comments
2021-09-23 Luke Kenneth Casso... add in a stack of comments for identifying match-points...
2021-09-23 Luke Kenneth Casso... add option to run ISACaller Sim (or not)
2021-09-23 Luke Kenneth Casso... add a new run_hdl parameter to TestRunner
2021-09-22 Luke Kenneth Casso... completely borked python segfault, workaround to copy...
2021-09-22 Luke Kenneth Casso... add test of expected results against last sim state
2021-09-22 Luke Kenneth Casso... whoops broken run_sim_state function
2021-09-22 Luke Kenneth Casso... split out HDL from Simulator into separate functions
2021-09-22 Luke Kenneth Casso... split out HDL test from Simulator test,
2021-09-22 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-22 Tobias Platencompldst_multi: add op_is_dcbz signal
2021-09-22 Jacob Lifshayfix mul fu test helper.py not passing immediate to...
2021-09-22 Tobias Platenwhitespace cleanup
2021-09-22 Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
2021-09-22 Luke Kenneth Casso... whoops forgot to do with self.subTest()
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platentestcase: add mmu, link mmu and dcache together
2021-09-21 klehmanchanged test_runner to use state mem compare
2021-09-21 klehmanchanged over to use state mem compare
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platencomment out lines that cause test_compldst_multi_mmu...
2021-09-21 Luke Kenneth Casso... convert HDLState.get_mem() to a dictionary of memory...
2021-09-20 Tobias Platenupdate test_compldst_multi_mmu.py
2021-09-20 Luke Kenneth Casso... use get_l0_mem in HDLState to get memory data
2021-09-19 Cesar StraussFix rel_o/go_i signal names
2021-09-19 Cesar StraussReplace "Display" with "print" on simulation process
2021-09-19 Cesar StraussFix import
2021-09-18 Luke Kenneth Casso... allow individual unit tests to be named in test_issuer.py
2021-09-18 Luke Kenneth Casso... always store full memory state (including zeros)
2021-09-18 klehmanadded get_mem
2021-09-17 Luke Kenneth Casso... update comments
2021-09-16 Luke Kenneth Casso... moving teststate_check_regs written by klehman into...
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-15 isengaaraadd new testcase for ompldst_multi using mmu
2021-09-14 Luke Kenneth Casso... convert to using TestState and State after moving to...
2021-09-14 klehmanfactory add and intro doc string
2021-09-12 Luke Kenneth Casso... use log instead of print
2021-09-12 Luke Kenneth Casso... code comments
2021-09-12 Luke Kenneth Casso... create new function teststate_check_regs which is calle...
2021-09-12 klehmanchanges to utilize full teststate class
2021-09-12 klehmanadded compare function
2021-09-12 klehmanadded factory function for test class creation
2021-09-10 klehmanimplement base class in state class
2021-09-10 klehmanchanges made to utilize teststate class
2021-09-10 Luke Kenneth Casso... update explanatory comments on LD/ST exception handling
2021-09-09 klehmanmade sim into generators and some uniformity changes
2021-09-09 klehmanfinished remaining hdl items
2021-09-09 klehmanHDL int reg added
2021-09-09 klehmanmore sim class registers add
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-09-08 klehmaninitial commit of sim state class
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-07 Luke Kenneth Casso... fun fixing of get_core_hdl_regs, "yield from"
2021-09-07 Luke Kenneth Casso... move functions to above where they are called
2021-09-07 klehmanbreakout of register collection and compare
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