use --recursive on git submodule not --remote - one does a "latest update"
[soclayout.git] / experiments / alu_hier.py
1 from nmigen import *
2 from nmigen.cli import rtlil
3
4
5 class Adder(Elaboratable):
6 def __init__(self, width):
7 self.a = Signal(width)
8 self.b = Signal(width)
9 self.o = Signal(width)
10
11 def elaborate(self, platform):
12 m = Module()
13 m.d.comb += self.o.eq(self.a + self.b)
14 return m
15
16
17 class Subtractor(Elaboratable):
18 def __init__(self, width):
19 self.a = Signal(width)
20 self.b = Signal(width)
21 self.o = Signal(width)
22
23 def elaborate(self, platform):
24 m = Module()
25 m.d.comb += self.o.eq(self.a - self.b)
26 return m
27
28
29 class ALU(Elaboratable):
30 def __init__(self, width):
31 self.op = Signal()
32 self.a = Signal(width)
33 self.b = Signal(width)
34 self.o = Signal(width)
35
36 self.add = Adder(width)
37 self.sub = Subtractor(width)
38
39 def elaborate(self, platform):
40
41 m = Module()
42 #m.domains.sync = ClockDomain()
43 #m.d.comb += ClockSignal().eq(self.m_clock)
44
45 m.submodules.add = self.add
46 m.submodules.sub = self.sub
47 m.d.comb += [
48 self.add.a.eq(self.a),
49 self.sub.a.eq(self.a),
50 self.add.b.eq(self.b),
51 self.sub.b.eq(self.b),
52 ]
53 with m.If(self.op):
54 m.d.sync += self.o.eq(self.sub.o)
55 with m.Else():
56 m.d.sync += self.o.eq(self.add.o)
57 return m
58
59
60 def create_ilang(dut, ports, test_name):
61 vl = rtlil.convert(dut, name=test_name, ports=ports)
62 with open("%s.il" % test_name, "w") as f:
63 f.write(vl)
64
65 if __name__ == "__main__":
66 alu = ALU(width=16)
67 create_ilang(alu, [#alu.m_clock, alu.p_reset,
68 alu.op, alu.a, alu.b, alu.o], "alu_hier")