experiments10/coriolis2/ioring.py

   1 #!/usr/bin/env python
   2
   3 from helpers import l, u, n
   4
   5
   6 chip = { 'pads.ioPadGauge' : 'pxlib',
   7
   8       #   | Instance  | Pad   | To Core          | From Core     | Enable    |
   9        'pads.instances' :[
  10         # "a" input.
  11         [ 'p_a0'    , 'a(0)', 'a(0)' ],
  12         [ 'p_a1'    , 'a(1)', 'a(1)' ],
  13         [ 'p_a2'    , 'a(2)', 'a(2)' ],
  14         [ 'p_a3'    , 'a(3)', 'a(3)' ],
  15         # "b" input.
  16         [ 'p_b0'    , 'b(0)', 'b(0)' ],
  17         [ 'p_b1'    , 'b(1)', 'b(1)' ],
  18         [ 'p_b2'    , 'b(2)', 'b(2)' ],
  19         [ 'p_b3'    , 'b(3)', 'b(3)' ],
  20         # "f" output.
  21         [ 'p_f0'    , 'f(0)',   'f(0)' ], # , 'f_oe' ],
  22         [ 'p_f1'    , 'f(1)',   'f(1)' ], # , 'f_oe' ],
  23         [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
  24         [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
  25         # JTAG
  26         [ 'p_tck_0'    , 'tck',   'tck'], # 2nd clock
  27         [ 'p_tms_0'    , 'tms',   'tms'],
  28         [ 'p_tdo_0'    , 'tdo',   'tdo'],
  29         [ 'p_tdi_0'    , 'tdi',   'tdi'],
  30         ],
  31         'pads.south'      :
  32             [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ],
  33        'pads.east'       :
  34             [ 'p_tck_0', # 2nd clock
  35                 'p_tms_0', 'p_tdo_0', 'p_tdi_0',
  36                 'p_b2'       ],
  37        'pads.north'      :
  38             [ 'p_b1', 'p_vddeck_0', 'p_b0', 'p_vsseck_0', 'rst' ],
  39        'pads.west'       :
  40             [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1' , 'p_f0', 'p_a3' ],
  41        'core.size'       : ( l( 1200), l( 1200) ),
  42        'chip.size'       : ( l(3200), l(3200) ),
  43        'pads.useCoreSize'  : True,
  44        'chip.clockTree'  : True,
  45        }
  46