use --recursive on git submodule not --remote - one does a "latest update"
[soclayout.git] / experiments12 / doDesign.py
1
2 from __future__ import print_function
3 import sys
4 import traceback
5 import collections
6 import CRL
7 import helpers
8 helpers.loadUserSettings()
9 from helpers import trace, l, u, n
10 from helpers.io import ErrorMessage, WarningMessage
11 from helpers.overlay import UpdateSession
12 import plugins
13 from Hurricane import Breakpoint, DbU, Transformation, Box, Instance
14 from plugins.alpha.macro.macro import Macro
15 from plugins.alpha.block.block import Block
16 from plugins.alpha.block.configuration import IoPin, GaugeConf
17 from plugins.alpha.core2chip.libresocio import CoreToChip
18 from plugins.alpha.chip.configuration import ChipConf
19 from plugins.alpha.chip.chip import Chip
20
21
22 af = CRL.AllianceFramework.get()
23
24
25 def isiterable ( pyobj ):
26 if isinstance(pyobj,collections.Iterable): return True
27 return False
28
29
30 def doIoPinVector ( ioSpec, bits ):
31 v = []
32 if not isiterable(bits): bits = range(bits)
33 if len(ioSpec) != 5:
34 raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "ioSpec" must have excatly 5 fields ({})'.format(len(ioSpec))
35 , '(ioSpec={})'.format(ioSpec)
36 ] )
37 if not bits:
38 raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "bits" is neither a width nor an iterable.'
39 , '(bits={})'.format(bits)
40 ] )
41 for bit in bits:
42 v.append(( ioSpec[0]
43 , ioSpec[1]
44 , ioSpec[2].format(bit)
45 , ioSpec[3].format(bit)
46 , ioSpec[4].format(bit) ))
47 return v
48
49
50 def scriptMain ( **kw ):
51 """The mandatory function to be called by Coriolis CGT/Unicorn."""
52 global af
53 rvalue = True
54 try:
55 #helpers.setTraceLevel( 550 )
56 Breakpoint.setStopLevel( 100 )
57 buildChip = True
58 cell, editor = plugins.kwParseMain( **kw )
59 cell = af.getCell( 'memory', CRL.Catalog.State.Logical )
60 if editor:
61 editor.setCell( cell )
62 editor.setDbuMode( DbU.StringModePhysical )
63
64 ioPadsSpec = []
65 ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'a_{}', 'a({})', 'a({})'), 8 )
66 ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'b_{}', 'b({})', 'b({})'), 8 )
67 ioPadsSpec += doIoPinVector( (IoPin.EAST , None, 'f_{}', 'f({})', 'f({})'), 8 )
68 ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'we_{}', 'we({})', 'we({})'), range(0,4) )
69 ioPadsSpec += [ (IoPin.NORTH, None, 'clk' , 'clk', 'clk' )
70 , (IoPin.NORTH, None, 'power_0' , 'vdd' )
71 , (IoPin.NORTH, None, 'ground_0' , 'vss' )
72 , (IoPin.NORTH, None, 'ioground_0', 'iovss' )
73 , (IoPin.NORTH, None, 'iopower_0' , 'iovdd' )
74 , (IoPin.NORTH, None, 'iopower_1' , 'iovdd' )
75 , (IoPin.NORTH, None, 'rst' , 'rst', 'rst' )
76 ]
77 ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'we_{}', 'we({})', 'we({})'), range(4,8) )
78 ioPinsSpec = [ (IoPin.WEST |IoPin.A_BEGIN, 'a({})' , u( 3.3), u( 6.6), 64)
79 , (IoPin.SOUTH|IoPin.A_BEGIN, 'b({})' , u( 3.3), u( 6.6), 64)
80 , (IoPin.EAST |IoPin.A_BEGIN, 'f({})' , u( 3.3), u( 6.6), 64)
81 , (IoPin.NORTH|IoPin.A_BEGIN, 'we({})' , u( 3.3), u( 6.6), 8)
82 , (IoPin.NORTH|IoPin.A_BEGIN, 'rst' , u( 33.0), 0 , 1)
83 , (IoPin.NORTH|IoPin.A_BEGIN, 'clk' , u( 66.0), 0 , 1)
84 ]
85 memoryConf = ChipConf( cell, ioPins=ioPinsSpec, ioPads=ioPadsSpec )
86 memoryConf.cfg.viewer.pixelThreshold = 5
87 memoryConf.cfg.etesian.bloat = 'nsxlib'
88 memoryConf.cfg.etesian.uniformDensity = True
89 memoryConf.cfg.etesian.aspectRatio = 1.0
90 # etesian.spaceMargin is ignored if the coreSize is directly set.
91 memoryConf.cfg.etesian.spaceMargin = 0.20
92 memoryConf.cfg.anabatic.searchHalo = 2
93 memoryConf.cfg.anabatic.globalIterations = 20
94 memoryConf.cfg.anabatic.topRoutingLayer = 'METAL5'
95 memoryConf.cfg.katana.hTracksReservedLocal = 6
96 memoryConf.cfg.katana.vTracksReservedLocal = 3
97 memoryConf.cfg.katana.hTracksReservedMin = 3
98 memoryConf.cfg.katana.vTracksReservedMin = 1
99 memoryConf.cfg.block.spareSide = u(200)
100 #memoryConf.cfg.chip.padCoreSide = 'North'
101 #memoryConf.cfg.chip.use45corners = False
102 memoryConf.cfg.chip.useAbstractPads = True
103 memoryConf.cfg.chip.supplyRailWidth = u(35)
104 memoryConf.cfg.chip.supplyRailPitch = u(90)
105 memoryConf.editor = editor
106 memoryConf.useSpares = True
107 memoryConf.useClockTree = True
108 memoryConf.useHFNS = False
109 memoryConf.bColumns = 2
110 memoryConf.bRows = 3
111 memoryConf.chipName = 'chip'
112 memoryConf.chipConf.ioPadGauge = 'LibreSOCIO'
113 memoryConf.coreSize = ( u( 988.0), u( 988.0) )
114 memoryConf.chipSize = ( u(2000.0), u(2000.0) )
115
116 with UpdateSession():
117 sliceHeight = memoryConf.sliceHeight
118 coreAb = Box( 0, 0, u(988.0), u(988.0) )
119 cell.setAbutmentBox( coreAb )
120 sramName = 'subckt_500_SPBlock_512W64B8W'
121 sram = cell.getInstance( sramName )
122 if not sram:
123 print( '[ERROR] SRAM instance "{}" not found.'.format(sramName) )
124 else:
125 Macro.wrap( sram.getMasterCell(), 'FlexLib', 3, 2 )
126 sramAb = sram.getMasterCell().getAbutmentBox()
127 Macro.place( sram
128 , Transformation( coreAb.getXMax() - sramAb.getWidth()
129 , u(0.0)
130 , Transformation.Orientation.ID )
131 , Instance.PlacementStatus.FIXED )
132 sramAb = sram.getAbutmentBox()
133 memoryConf.placeArea = Box( coreAb.getXMin()
134 , coreAb.getYMax() - sliceHeight*26
135 , coreAb.getXMin() + sliceHeight*25
136 , coreAb.getYMax()
137 )
138 Breakpoint.stop( 99, 'After core block placement.' )
139
140 if buildChip:
141 memoryToChip = CoreToChip( memoryConf )
142 memoryToChip.buildChip()
143 chipBuilder = Chip( memoryConf )
144 rvalue = chipBuilder.doPnR()
145 chipBuilder.save()
146 CRL.Gds.save( memoryConf.chip )
147 else:
148 blockBuilder = Block( memoryConf )
149 rvalue = blockBuilder.doPnR()
150 blockBuilder.save()
151 CRL.Gds.save( memoryConf.cell )
152 except Exception, e:
153 helpers.io.catch( e )
154 rvalue = False
155 sys.stdout.flush()
156 sys.stderr.flush()
157 return rvalue