experiments12/memory.py

   1 from nmigen import Elaboratable, Cat, Module, Signal, ClockSignal, Instance
   2 from nmigen.cli import rtlil
   3
   4
   5 class ADD(Elaboratable):
   6     def __init__(self, width):
   7         self.we  = Signal(8)
   8         self.a   = Signal(width)
   9         self.b   = Signal(width)
  10         self.f   = Signal(width)
  11
  12     def elaborate(self, platform):
  13         m = Module()
  14         result = Signal.like(self.f)
  15         m.d.sync += result.eq(self.a + self.b)
  16
  17         # 64k SRAM instance
  18         a = Signal(9)
  19         q = Signal(64) # output
  20         d = Signal(64) # input
  21         sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
  22                                              i_we=self.we, i_clk=ClockSignal())
  23         m.submodules += sram
  24
  25         # connect up some arbitrary signals
  26         m.d.comb += a.eq(Cat(self.a, self.b, self.a[0]))
  27         m.d.comb += d.eq(result)
  28         m.d.comb += self.f.eq(q)
  29
  30         return m
  31
  32
  33 def create_ilang(dut, ports, test_name):
  34     vl = rtlil.convert(dut, name=test_name, ports=ports)
  35     with open("%s.il" % test_name, "w") as f:
  36         f.write(vl)
  37
  38 if __name__ == "__main__":
  39     alu = ADD(width=64)
  40     create_ilang(alu, [alu.a, alu.b, alu.f, alu.we], "memory")