experiments12/memory.py

   1 from nmigen import *
   2 from nmigen.cli import rtlil
   3
   4
   5 class ADD(Elaboratable):
   6     def __init__(self, width):
   7         self.a   = Signal(width)
   8         self.b   = Signal(width)
   9         self.f   = Signal(width)
  10
  11     def elaborate(self, platform):
  12         m = Module()
  13         m.d.sync += self.f.eq(self.a + self.b)
  14         #a = Signal(9)
  15         #q = Signal(64)
  16         #d = Signal(64)
  17         #we = Signal(8)
  18         #sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
  19         #m.submodules += sram
  20         return m
  21
  22
  23 def create_ilang(dut, ports, test_name):
  24     vl = rtlil.convert(dut, name=test_name, ports=ports)
  25     with open("%s.il" % test_name, "w") as f:
  26         f.write(vl)
  27
  28 if __name__ == "__main__":
  29     alu = ADD(width=4)
  30     create_ilang(alu, [alu.a, alu.b, alu.f], "memory")