experiments7/Makefile

   1        LOGICAL_SYNTHESIS = Yosys
   2        PHYSICAL_SYNTHESIS = Coriolis
   3                DESIGN_KIT = sxlib
   4
   5             USE_CLOCKTREE = No
   6                 USE_DEBUG = No
   7                  USE_KITE = No
   8
   9                  NETLISTS = alu16 \
  10                             add   \
  11                             sub
  12                  PATTERNS = alu16_r
  13
  14
  15  include ./mk/design-flow.mk
  16
  17
  18 blif:      alu16.blif
  19 vst:       alu16.vst
  20 layout:    alu16_r.ap
  21 gds:       alu16_r.gds
  22
  23 lvx:       lvx-alu16_r
  24 druc:      druc-alu16_r
  25 view:      cgt-alu16_r
  26 sim:       asimut-alu16_r