experiments8/test_mem_fus.il

   1 attribute \generator "nMigen"
   2 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.war_l"
   3 module \war_l
   4   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
   5   wire width 8 input 0 \s
   6   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   7   wire width 8 input 1 \r
   8   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   9   wire width 8 output 2 \qn
  10   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  11   wire width 1 input 3 \rst
  12   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  13   wire width 1 input 4 \clk
  14   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  15   wire width 8 \q_int
  16   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  17   wire width 8 \q_int$next
  18   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  19   wire width 8 $1
  20   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  21   cell $not $2
  22     parameter \A_SIGNED 1'0
  23     parameter \A_WIDTH 4'1000
  24     parameter \Y_WIDTH 4'1000
  25     connect \A \r
  26     connect \Y $1
  27   end
  28   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  29   wire width 8 $3
  30   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  31   cell $and $4
  32     parameter \A_SIGNED 1'0
  33     parameter \A_WIDTH 4'1000
  34     parameter \B_SIGNED 1'0
  35     parameter \B_WIDTH 4'1000
  36     parameter \Y_WIDTH 4'1000
  37     connect \A \q_int
  38     connect \B $1
  39     connect \Y $3
  40   end
  41   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  42   wire width 8 $5
  43   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  44   cell $or $6
  45     parameter \A_SIGNED 1'0
  46     parameter \A_WIDTH 4'1000
  47     parameter \B_SIGNED 1'0
  48     parameter \B_WIDTH 4'1000
  49     parameter \Y_WIDTH 4'1000
  50     connect \A $3
  51     connect \B \s
  52     connect \Y $5
  53   end
  54   process $group_0
  55     assign \q_int$next \q_int
  56     assign \q_int$next $5
  57     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
  58     switch \rst
  59       case 1'1
  60         assign \q_int$next 8'00000000
  61     end
  62     sync init
  63       update \q_int 8'00000000
  64     sync posedge \clk
  65       update \q_int \q_int$next
  66   end
  67   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  68   wire width 8 \q
  69   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  70   wire width 8 $7
  71   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  72   cell $not $8
  73     parameter \A_SIGNED 1'0
  74     parameter \A_WIDTH 4'1000
  75     parameter \Y_WIDTH 4'1000
  76     connect \A \r
  77     connect \Y $7
  78   end
  79   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  80   wire width 8 $9
  81   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  82   cell $and $10
  83     parameter \A_SIGNED 1'0
  84     parameter \A_WIDTH 4'1000
  85     parameter \B_SIGNED 1'0
  86     parameter \B_WIDTH 4'1000
  87     parameter \Y_WIDTH 4'1000
  88     connect \A \q_int
  89     connect \B $7
  90     connect \Y $9
  91   end
  92   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  93   wire width 8 $11
  94   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  95   cell $or $12
  96     parameter \A_SIGNED 1'0
  97     parameter \A_WIDTH 4'1000
  98     parameter \B_SIGNED 1'0
  99     parameter \B_WIDTH 4'1000
 100     parameter \Y_WIDTH 4'1000
 101     connect \A $9
 102     connect \B \s
 103     connect \Y $11
 104   end
 105   process $group_1
 106     assign \q 8'00000000
 107     assign \q $11
 108     sync init
 109   end
 110   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 111   wire width 8 $13
 112   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 113   cell $not $14
 114     parameter \A_SIGNED 1'0
 115     parameter \A_WIDTH 4'1000
 116     parameter \Y_WIDTH 4'1000
 117     connect \A \q
 118     connect \Y $13
 119   end
 120   process $group_2
 121     assign \qn 8'00000000
 122     assign \qn $13
 123     sync init
 124   end
 125   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 126   wire width 8 \qlq
 127   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 128   wire width 8 $15
 129   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 130   cell $or $16
 131     parameter \A_SIGNED 1'0
 132     parameter \A_WIDTH 4'1000
 133     parameter \B_SIGNED 1'0
 134     parameter \B_WIDTH 4'1000
 135     parameter \Y_WIDTH 4'1000
 136     connect \A \q
 137     connect \B \q_int
 138     connect \Y $15
 139   end
 140   process $group_3
 141     assign \qlq 8'00000000
 142     assign \qlq $15
 143     sync init
 144   end
 145 end
 146 attribute \generator "nMigen"
 147 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.raw_l"
 148 module \raw_l
 149   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 150   wire width 8 input 0 \s
 151   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 152   wire width 8 input 1 \r
 153   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 154   wire width 8 output 2 \qn
 155   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 156   wire width 1 input 3 \rst
 157   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 158   wire width 1 input 4 \clk
 159   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 160   wire width 8 \q_int
 161   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 162   wire width 8 \q_int$next
 163   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 164   wire width 8 $1
 165   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 166   cell $not $2
 167     parameter \A_SIGNED 1'0
 168     parameter \A_WIDTH 4'1000
 169     parameter \Y_WIDTH 4'1000
 170     connect \A \r
 171     connect \Y $1
 172   end
 173   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 174   wire width 8 $3
 175   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 176   cell $and $4
 177     parameter \A_SIGNED 1'0
 178     parameter \A_WIDTH 4'1000
 179     parameter \B_SIGNED 1'0
 180     parameter \B_WIDTH 4'1000
 181     parameter \Y_WIDTH 4'1000
 182     connect \A \q_int
 183     connect \B $1
 184     connect \Y $3
 185   end
 186   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 187   wire width 8 $5
 188   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 189   cell $or $6
 190     parameter \A_SIGNED 1'0
 191     parameter \A_WIDTH 4'1000
 192     parameter \B_SIGNED 1'0
 193     parameter \B_WIDTH 4'1000
 194     parameter \Y_WIDTH 4'1000
 195     connect \A $3
 196     connect \B \s
 197     connect \Y $5
 198   end
 199   process $group_0
 200     assign \q_int$next \q_int
 201     assign \q_int$next $5
 202     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 203     switch \rst
 204       case 1'1
 205         assign \q_int$next 8'00000000
 206     end
 207     sync init
 208       update \q_int 8'00000000
 209     sync posedge \clk
 210       update \q_int \q_int$next
 211   end
 212   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 213   wire width 8 \q
 214   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 215   wire width 8 $7
 216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 217   cell $not $8
 218     parameter \A_SIGNED 1'0
 219     parameter \A_WIDTH 4'1000
 220     parameter \Y_WIDTH 4'1000
 221     connect \A \r
 222     connect \Y $7
 223   end
 224   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 225   wire width 8 $9
 226   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 227   cell $and $10
 228     parameter \A_SIGNED 1'0
 229     parameter \A_WIDTH 4'1000
 230     parameter \B_SIGNED 1'0
 231     parameter \B_WIDTH 4'1000
 232     parameter \Y_WIDTH 4'1000
 233     connect \A \q_int
 234     connect \B $7
 235     connect \Y $9
 236   end
 237   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 238   wire width 8 $11
 239   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 240   cell $or $12
 241     parameter \A_SIGNED 1'0
 242     parameter \A_WIDTH 4'1000
 243     parameter \B_SIGNED 1'0
 244     parameter \B_WIDTH 4'1000
 245     parameter \Y_WIDTH 4'1000
 246     connect \A $9
 247     connect \B \s
 248     connect \Y $11
 249   end
 250   process $group_1
 251     assign \q 8'00000000
 252     assign \q $11
 253     sync init
 254   end
 255   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 256   wire width 8 $13
 257   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 258   cell $not $14
 259     parameter \A_SIGNED 1'0
 260     parameter \A_WIDTH 4'1000
 261     parameter \Y_WIDTH 4'1000
 262     connect \A \q
 263     connect \Y $13
 264   end
 265   process $group_2
 266     assign \qn 8'00000000
 267     assign \qn $13
 268     sync init
 269   end
 270   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 271   wire width 8 \qlq
 272   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 273   wire width 8 $15
 274   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 275   cell $or $16
 276     parameter \A_SIGNED 1'0
 277     parameter \A_WIDTH 4'1000
 278     parameter \B_SIGNED 1'0
 279     parameter \B_WIDTH 4'1000
 280     parameter \Y_WIDTH 4'1000
 281     connect \A \q
 282     connect \B \q_int
 283     connect \Y $15
 284   end
 285   process $group_3
 286     assign \qlq 8'00000000
 287     assign \qlq $15
 288     sync init
 289   end
 290 end
 291 attribute \generator "nMigen"
 292 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0"
 293 module \dm_fu0
 294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
 295   wire width 8 input 0 \load_hit_i
 296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
 297   wire width 8 input 1 \stwd_hit_i
 298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
 299   wire width 8 input 2 \load_v_i
 300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
 301   wire width 8 input 3 \stor_v_i
 302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
 303   wire width 1 input 4 \issue_i
 304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
 305   wire width 1 input 5 \go_die_i
 306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
 307   wire width 1 output 6 \ld_hold_st_o
 308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
 309   wire width 1 output 7 \st_hold_ld_o
 310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
 311   wire width 1 input 8 \load_h_i
 312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
 313   wire width 1 input 9 \stor_h_i
 314   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 315   wire width 1 input 10 \rst
 316   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 317   wire width 1 input 11 \clk
 318   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 319   wire width 8 \war_l_s
 320   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 321   wire width 8 \war_l_r
 322   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 323   wire width 8 \war_l_qn
 324   cell \war_l \war_l
 325     connect \s \war_l_s
 326     connect \r \war_l_r
 327     connect \qn \war_l_qn
 328     connect \rst \rst
 329     connect \clk \clk
 330   end
 331   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 332   wire width 8 \raw_l_s
 333   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 334   wire width 8 \raw_l_r
 335   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 336   wire width 8 \raw_l_qn
 337   cell \raw_l \raw_l
 338     connect \s \raw_l_s
 339     connect \r \raw_l_r
 340     connect \qn \raw_l_qn
 341     connect \rst \rst
 342     connect \clk \clk
 343   end
 344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
 345   wire width 1 \i_s
 346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 347   wire width 8 $1
 348   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 349   wire width 8 $2
 350   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 351   cell $and $3
 352     parameter \A_SIGNED 1'0
 353     parameter \A_WIDTH 4'1000
 354     parameter \B_SIGNED 1'0
 355     parameter \B_WIDTH 1'1
 356     parameter \Y_WIDTH 4'1000
 357     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
 358     connect \B \stor_h_i
 359     connect \Y $2
 360   end
 361   connect $1 $2
 362   process $group_0
 363     assign \i_s 1'0
 364     assign \i_s $1 [0]
 365     sync init
 366   end
 367   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
 368   wire width 8 \i_s_l
 369   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
 370   wire width 8 $4
 371   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
 372   cell $and $5
 373     parameter \A_SIGNED 1'0
 374     parameter \A_WIDTH 4'1000
 375     parameter \B_SIGNED 1'0
 376     parameter \B_WIDTH 4'1000
 377     parameter \Y_WIDTH 4'1000
 378     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
 379     connect \B \load_v_i
 380     connect \Y $4
 381   end
 382   process $group_1
 383     assign \i_s_l 8'00000000
 384     assign \i_s_l $4
 385     sync init
 386   end
 387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
 388   wire width 1 \i_l
 389   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 390   wire width 8 $6
 391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 392   wire width 8 $7
 393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 394   cell $and $8
 395     parameter \A_SIGNED 1'0
 396     parameter \A_WIDTH 4'1000
 397     parameter \B_SIGNED 1'0
 398     parameter \B_WIDTH 1'1
 399     parameter \Y_WIDTH 4'1000
 400     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
 401     connect \B \load_h_i
 402     connect \Y $7
 403   end
 404   connect $6 $7
 405   process $group_2
 406     assign \i_l 1'0
 407     assign \i_l $6 [0]
 408     sync init
 409   end
 410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
 411   wire width 8 \i_l_s
 412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
 413   wire width 8 $9
 414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
 415   cell $and $10
 416     parameter \A_SIGNED 1'0
 417     parameter \A_WIDTH 4'1000
 418     parameter \B_SIGNED 1'0
 419     parameter \B_WIDTH 4'1000
 420     parameter \Y_WIDTH 4'1000
 421     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
 422     connect \B \stor_v_i
 423     connect \Y $9
 424   end
 425   process $group_3
 426     assign \i_l_s 8'00000000
 427     assign \i_l_s $9
 428     sync init
 429   end
 430   process $group_4
 431     assign \war_l_s 8'00000000
 432     assign \war_l_s \i_s_l
 433     sync init
 434   end
 435   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 436   wire width 8 $11
 437   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 438   cell $not $12
 439     parameter \A_SIGNED 1'0
 440     parameter \A_WIDTH 4'1000
 441     parameter \Y_WIDTH 4'1000
 442     connect \A \load_v_i
 443     connect \Y $11
 444   end
 445   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 446   wire width 8 $13
 447   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 448   cell $or $14
 449     parameter \A_SIGNED 1'0
 450     parameter \A_WIDTH 4'1000
 451     parameter \B_SIGNED 1'0
 452     parameter \B_WIDTH 4'1000
 453     parameter \Y_WIDTH 4'1000
 454     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
 455     connect \B $11
 456     connect \Y $13
 457   end
 458   process $group_5
 459     assign \war_l_r 8'11111111
 460     assign \war_l_r $13
 461     sync init
 462   end
 463   process $group_6
 464     assign \raw_l_s 8'00000000
 465     assign \raw_l_s \i_s_l
 466     sync init
 467   end
 468   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
 469   wire width 8 $15
 470   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
 471   cell $not $16
 472     parameter \A_SIGNED 1'0
 473     parameter \A_WIDTH 4'1000
 474     parameter \Y_WIDTH 4'1000
 475     connect \A \stor_v_i
 476     connect \Y $15
 477   end
 478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
 479   wire width 8 $17
 480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
 481   cell $or $18
 482     parameter \A_SIGNED 1'0
 483     parameter \A_WIDTH 4'1000
 484     parameter \B_SIGNED 1'0
 485     parameter \B_WIDTH 4'1000
 486     parameter \Y_WIDTH 4'1000
 487     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
 488     connect \B $15
 489     connect \Y $17
 490   end
 491   process $group_7
 492     assign \raw_l_r 8'11111111
 493     assign \raw_l_r $17
 494     sync init
 495   end
 496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
 497   wire width 1 $19
 498   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
 499   wire width 8 $20
 500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
 501   cell $and $21
 502     parameter \A_SIGNED 1'0
 503     parameter \A_WIDTH 4'1000
 504     parameter \B_SIGNED 1'0
 505     parameter \B_WIDTH 4'1000
 506     parameter \Y_WIDTH 4'1000
 507     connect \A \war_l_qn
 508     connect \B \load_hit_i
 509     connect \Y $20
 510   end
 511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
 512   cell $reduce_bool $22
 513     parameter \A_SIGNED 1'0
 514     parameter \A_WIDTH 4'1000
 515     parameter \Y_WIDTH 1'1
 516     connect \A $20
 517     connect \Y $19
 518   end
 519   process $group_8
 520     assign \ld_hold_st_o 1'0
 521     assign \ld_hold_st_o $19
 522     sync init
 523   end
 524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
 525   wire width 1 $23
 526   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
 527   wire width 8 $24
 528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
 529   cell $and $25
 530     parameter \A_SIGNED 1'0
 531     parameter \A_WIDTH 4'1000
 532     parameter \B_SIGNED 1'0
 533     parameter \B_WIDTH 4'1000
 534     parameter \Y_WIDTH 4'1000
 535     connect \A \raw_l_qn
 536     connect \B \stwd_hit_i
 537     connect \Y $24
 538   end
 539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
 540   cell $reduce_bool $26
 541     parameter \A_SIGNED 1'0
 542     parameter \A_WIDTH 4'1000
 543     parameter \Y_WIDTH 1'1
 544     connect \A $24
 545     connect \Y $23
 546   end
 547   process $group_9
 548     assign \st_hold_ld_o 1'0
 549     assign \st_hold_ld_o $23
 550     sync init
 551   end
 552 end
 553 attribute \generator "nMigen"
 554 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.war_l"
 555 module \war_l$1
 556   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 557   wire width 1 input 0 \rst
 558   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 559   wire width 1 input 1 \clk
 560   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 561   wire width 8 input 2 \s
 562   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 563   wire width 8 input 3 \r
 564   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 565   wire width 8 output 4 \qn
 566   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 567   wire width 8 \q_int
 568   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 569   wire width 8 \q_int$next
 570   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 571   wire width 8 $1
 572   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 573   cell $not $2
 574     parameter \A_SIGNED 1'0
 575     parameter \A_WIDTH 4'1000
 576     parameter \Y_WIDTH 4'1000
 577     connect \A \r
 578     connect \Y $1
 579   end
 580   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 581   wire width 8 $3
 582   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 583   cell $and $4
 584     parameter \A_SIGNED 1'0
 585     parameter \A_WIDTH 4'1000
 586     parameter \B_SIGNED 1'0
 587     parameter \B_WIDTH 4'1000
 588     parameter \Y_WIDTH 4'1000
 589     connect \A \q_int
 590     connect \B $1
 591     connect \Y $3
 592   end
 593   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 594   wire width 8 $5
 595   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 596   cell $or $6
 597     parameter \A_SIGNED 1'0
 598     parameter \A_WIDTH 4'1000
 599     parameter \B_SIGNED 1'0
 600     parameter \B_WIDTH 4'1000
 601     parameter \Y_WIDTH 4'1000
 602     connect \A $3
 603     connect \B \s
 604     connect \Y $5
 605   end
 606   process $group_0
 607     assign \q_int$next \q_int
 608     assign \q_int$next $5
 609     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 610     switch \rst
 611       case 1'1
 612         assign \q_int$next 8'00000000
 613     end
 614     sync init
 615       update \q_int 8'00000000
 616     sync posedge \clk
 617       update \q_int \q_int$next
 618   end
 619   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 620   wire width 8 \q
 621   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 622   wire width 8 $7
 623   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 624   cell $not $8
 625     parameter \A_SIGNED 1'0
 626     parameter \A_WIDTH 4'1000
 627     parameter \Y_WIDTH 4'1000
 628     connect \A \r
 629     connect \Y $7
 630   end
 631   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 632   wire width 8 $9
 633   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 634   cell $and $10
 635     parameter \A_SIGNED 1'0
 636     parameter \A_WIDTH 4'1000
 637     parameter \B_SIGNED 1'0
 638     parameter \B_WIDTH 4'1000
 639     parameter \Y_WIDTH 4'1000
 640     connect \A \q_int
 641     connect \B $7
 642     connect \Y $9
 643   end
 644   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 645   wire width 8 $11
 646   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 647   cell $or $12
 648     parameter \A_SIGNED 1'0
 649     parameter \A_WIDTH 4'1000
 650     parameter \B_SIGNED 1'0
 651     parameter \B_WIDTH 4'1000
 652     parameter \Y_WIDTH 4'1000
 653     connect \A $9
 654     connect \B \s
 655     connect \Y $11
 656   end
 657   process $group_1
 658     assign \q 8'00000000
 659     assign \q $11
 660     sync init
 661   end
 662   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 663   wire width 8 $13
 664   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 665   cell $not $14
 666     parameter \A_SIGNED 1'0
 667     parameter \A_WIDTH 4'1000
 668     parameter \Y_WIDTH 4'1000
 669     connect \A \q
 670     connect \Y $13
 671   end
 672   process $group_2
 673     assign \qn 8'00000000
 674     assign \qn $13
 675     sync init
 676   end
 677   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 678   wire width 8 \qlq
 679   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 680   wire width 8 $15
 681   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 682   cell $or $16
 683     parameter \A_SIGNED 1'0
 684     parameter \A_WIDTH 4'1000
 685     parameter \B_SIGNED 1'0
 686     parameter \B_WIDTH 4'1000
 687     parameter \Y_WIDTH 4'1000
 688     connect \A \q
 689     connect \B \q_int
 690     connect \Y $15
 691   end
 692   process $group_3
 693     assign \qlq 8'00000000
 694     assign \qlq $15
 695     sync init
 696   end
 697 end
 698 attribute \generator "nMigen"
 699 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.raw_l"
 700 module \raw_l$2
 701   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 702   wire width 1 input 0 \rst
 703   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 704   wire width 1 input 1 \clk
 705   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 706   wire width 8 input 2 \s
 707   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 708   wire width 8 input 3 \r
 709   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 710   wire width 8 output 4 \qn
 711   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 712   wire width 8 \q_int
 713   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 714   wire width 8 \q_int$next
 715   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 716   wire width 8 $1
 717   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 718   cell $not $2
 719     parameter \A_SIGNED 1'0
 720     parameter \A_WIDTH 4'1000
 721     parameter \Y_WIDTH 4'1000
 722     connect \A \r
 723     connect \Y $1
 724   end
 725   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 726   wire width 8 $3
 727   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 728   cell $and $4
 729     parameter \A_SIGNED 1'0
 730     parameter \A_WIDTH 4'1000
 731     parameter \B_SIGNED 1'0
 732     parameter \B_WIDTH 4'1000
 733     parameter \Y_WIDTH 4'1000
 734     connect \A \q_int
 735     connect \B $1
 736     connect \Y $3
 737   end
 738   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 739   wire width 8 $5
 740   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 741   cell $or $6
 742     parameter \A_SIGNED 1'0
 743     parameter \A_WIDTH 4'1000
 744     parameter \B_SIGNED 1'0
 745     parameter \B_WIDTH 4'1000
 746     parameter \Y_WIDTH 4'1000
 747     connect \A $3
 748     connect \B \s
 749     connect \Y $5
 750   end
 751   process $group_0
 752     assign \q_int$next \q_int
 753     assign \q_int$next $5
 754     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 755     switch \rst
 756       case 1'1
 757         assign \q_int$next 8'00000000
 758     end
 759     sync init
 760       update \q_int 8'00000000
 761     sync posedge \clk
 762       update \q_int \q_int$next
 763   end
 764   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 765   wire width 8 \q
 766   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 767   wire width 8 $7
 768   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 769   cell $not $8
 770     parameter \A_SIGNED 1'0
 771     parameter \A_WIDTH 4'1000
 772     parameter \Y_WIDTH 4'1000
 773     connect \A \r
 774     connect \Y $7
 775   end
 776   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 777   wire width 8 $9
 778   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 779   cell $and $10
 780     parameter \A_SIGNED 1'0
 781     parameter \A_WIDTH 4'1000
 782     parameter \B_SIGNED 1'0
 783     parameter \B_WIDTH 4'1000
 784     parameter \Y_WIDTH 4'1000
 785     connect \A \q_int
 786     connect \B $7
 787     connect \Y $9
 788   end
 789   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 790   wire width 8 $11
 791   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 792   cell $or $12
 793     parameter \A_SIGNED 1'0
 794     parameter \A_WIDTH 4'1000
 795     parameter \B_SIGNED 1'0
 796     parameter \B_WIDTH 4'1000
 797     parameter \Y_WIDTH 4'1000
 798     connect \A $9
 799     connect \B \s
 800     connect \Y $11
 801   end
 802   process $group_1
 803     assign \q 8'00000000
 804     assign \q $11
 805     sync init
 806   end
 807   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 808   wire width 8 $13
 809   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 810   cell $not $14
 811     parameter \A_SIGNED 1'0
 812     parameter \A_WIDTH 4'1000
 813     parameter \Y_WIDTH 4'1000
 814     connect \A \q
 815     connect \Y $13
 816   end
 817   process $group_2
 818     assign \qn 8'00000000
 819     assign \qn $13
 820     sync init
 821   end
 822   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 823   wire width 8 \qlq
 824   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 825   wire width 8 $15
 826   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 827   cell $or $16
 828     parameter \A_SIGNED 1'0
 829     parameter \A_WIDTH 4'1000
 830     parameter \B_SIGNED 1'0
 831     parameter \B_WIDTH 4'1000
 832     parameter \Y_WIDTH 4'1000
 833     connect \A \q
 834     connect \B \q_int
 835     connect \Y $15
 836   end
 837   process $group_3
 838     assign \qlq 8'00000000
 839     assign \qlq $15
 840     sync init
 841   end
 842 end
 843 attribute \generator "nMigen"
 844 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1"
 845 module \dm_fu1
 846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
 847   wire width 8 input 0 \load_hit_i
 848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
 849   wire width 8 input 1 \stwd_hit_i
 850   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
 851   wire width 8 input 2 \load_v_i
 852   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
 853   wire width 8 input 3 \stor_v_i
 854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
 855   wire width 1 input 4 \issue_i
 856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
 857   wire width 1 input 5 \go_die_i
 858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
 859   wire width 1 output 6 \ld_hold_st_o
 860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
 861   wire width 1 output 7 \st_hold_ld_o
 862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
 863   wire width 1 input 8 \load_h_i
 864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
 865   wire width 1 input 9 \stor_h_i
 866   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 867   wire width 1 input 10 \rst
 868   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 869   wire width 1 input 11 \clk
 870   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 871   wire width 8 \war_l_s
 872   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 873   wire width 8 \war_l_r
 874   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 875   wire width 8 \war_l_qn
 876   cell \war_l$1 \war_l
 877     connect \rst \rst
 878     connect \clk \clk
 879     connect \s \war_l_s
 880     connect \r \war_l_r
 881     connect \qn \war_l_qn
 882   end
 883   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 884   wire width 8 \raw_l_s
 885   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 886   wire width 8 \raw_l_r
 887   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 888   wire width 8 \raw_l_qn
 889   cell \raw_l$2 \raw_l
 890     connect \rst \rst
 891     connect \clk \clk
 892     connect \s \raw_l_s
 893     connect \r \raw_l_r
 894     connect \qn \raw_l_qn
 895   end
 896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
 897   wire width 1 \i_s
 898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 899   wire width 8 $1
 900   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 901   wire width 8 $2
 902   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
 903   cell $and $3
 904     parameter \A_SIGNED 1'0
 905     parameter \A_WIDTH 4'1000
 906     parameter \B_SIGNED 1'0
 907     parameter \B_WIDTH 1'1
 908     parameter \Y_WIDTH 4'1000
 909     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
 910     connect \B \stor_h_i
 911     connect \Y $2
 912   end
 913   connect $1 $2
 914   process $group_0
 915     assign \i_s 1'0
 916     assign \i_s $1 [0]
 917     sync init
 918   end
 919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
 920   wire width 8 \i_s_l
 921   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
 922   wire width 8 $4
 923   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
 924   cell $and $5
 925     parameter \A_SIGNED 1'0
 926     parameter \A_WIDTH 4'1000
 927     parameter \B_SIGNED 1'0
 928     parameter \B_WIDTH 4'1000
 929     parameter \Y_WIDTH 4'1000
 930     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
 931     connect \B \load_v_i
 932     connect \Y $4
 933   end
 934   process $group_1
 935     assign \i_s_l 8'00000000
 936     assign \i_s_l $4
 937     sync init
 938   end
 939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
 940   wire width 1 \i_l
 941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 942   wire width 8 $6
 943   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 944   wire width 8 $7
 945   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
 946   cell $and $8
 947     parameter \A_SIGNED 1'0
 948     parameter \A_WIDTH 4'1000
 949     parameter \B_SIGNED 1'0
 950     parameter \B_WIDTH 1'1
 951     parameter \Y_WIDTH 4'1000
 952     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
 953     connect \B \load_h_i
 954     connect \Y $7
 955   end
 956   connect $6 $7
 957   process $group_2
 958     assign \i_l 1'0
 959     assign \i_l $6 [0]
 960     sync init
 961   end
 962   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
 963   wire width 8 \i_l_s
 964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
 965   wire width 8 $9
 966   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
 967   cell $and $10
 968     parameter \A_SIGNED 1'0
 969     parameter \A_WIDTH 4'1000
 970     parameter \B_SIGNED 1'0
 971     parameter \B_WIDTH 4'1000
 972     parameter \Y_WIDTH 4'1000
 973     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
 974     connect \B \stor_v_i
 975     connect \Y $9
 976   end
 977   process $group_3
 978     assign \i_l_s 8'00000000
 979     assign \i_l_s $9
 980     sync init
 981   end
 982   process $group_4
 983     assign \war_l_s 8'00000000
 984     assign \war_l_s \i_s_l
 985     sync init
 986   end
 987   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 988   wire width 8 $11
 989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 990   cell $not $12
 991     parameter \A_SIGNED 1'0
 992     parameter \A_WIDTH 4'1000
 993     parameter \Y_WIDTH 4'1000
 994     connect \A \load_v_i
 995     connect \Y $11
 996   end
 997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
 998   wire width 8 $13
 999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1000   cell $or $14
1001     parameter \A_SIGNED 1'0
1002     parameter \A_WIDTH 4'1000
1003     parameter \B_SIGNED 1'0
1004     parameter \B_WIDTH 4'1000
1005     parameter \Y_WIDTH 4'1000
1006     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1007     connect \B $11
1008     connect \Y $13
1009   end
1010   process $group_5
1011     assign \war_l_r 8'11111111
1012     assign \war_l_r $13
1013     sync init
1014   end
1015   process $group_6
1016     assign \raw_l_s 8'00000000
1017     assign \raw_l_s \i_s_l
1018     sync init
1019   end
1020   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1021   wire width 8 $15
1022   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1023   cell $not $16
1024     parameter \A_SIGNED 1'0
1025     parameter \A_WIDTH 4'1000
1026     parameter \Y_WIDTH 4'1000
1027     connect \A \stor_v_i
1028     connect \Y $15
1029   end
1030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1031   wire width 8 $17
1032   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1033   cell $or $18
1034     parameter \A_SIGNED 1'0
1035     parameter \A_WIDTH 4'1000
1036     parameter \B_SIGNED 1'0
1037     parameter \B_WIDTH 4'1000
1038     parameter \Y_WIDTH 4'1000
1039     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1040     connect \B $15
1041     connect \Y $17
1042   end
1043   process $group_7
1044     assign \raw_l_r 8'11111111
1045     assign \raw_l_r $17
1046     sync init
1047   end
1048   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1049   wire width 1 $19
1050   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1051   wire width 8 $20
1052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1053   cell $and $21
1054     parameter \A_SIGNED 1'0
1055     parameter \A_WIDTH 4'1000
1056     parameter \B_SIGNED 1'0
1057     parameter \B_WIDTH 4'1000
1058     parameter \Y_WIDTH 4'1000
1059     connect \A \war_l_qn
1060     connect \B \load_hit_i
1061     connect \Y $20
1062   end
1063   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1064   cell $reduce_bool $22
1065     parameter \A_SIGNED 1'0
1066     parameter \A_WIDTH 4'1000
1067     parameter \Y_WIDTH 1'1
1068     connect \A $20
1069     connect \Y $19
1070   end
1071   process $group_8
1072     assign \ld_hold_st_o 1'0
1073     assign \ld_hold_st_o $19
1074     sync init
1075   end
1076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1077   wire width 1 $23
1078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1079   wire width 8 $24
1080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1081   cell $and $25
1082     parameter \A_SIGNED 1'0
1083     parameter \A_WIDTH 4'1000
1084     parameter \B_SIGNED 1'0
1085     parameter \B_WIDTH 4'1000
1086     parameter \Y_WIDTH 4'1000
1087     connect \A \raw_l_qn
1088     connect \B \stwd_hit_i
1089     connect \Y $24
1090   end
1091   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1092   cell $reduce_bool $26
1093     parameter \A_SIGNED 1'0
1094     parameter \A_WIDTH 4'1000
1095     parameter \Y_WIDTH 1'1
1096     connect \A $24
1097     connect \Y $23
1098   end
1099   process $group_9
1100     assign \st_hold_ld_o 1'0
1101     assign \st_hold_ld_o $23
1102     sync init
1103   end
1104 end
1105 attribute \generator "nMigen"
1106 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.war_l"
1107 module \war_l$3
1108   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1109   wire width 1 input 0 \rst
1110   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1111   wire width 1 input 1 \clk
1112   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1113   wire width 8 input 2 \s
1114   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1115   wire width 8 input 3 \r
1116   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1117   wire width 8 output 4 \qn
1118   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1119   wire width 8 \q_int
1120   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1121   wire width 8 \q_int$next
1122   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1123   wire width 8 $1
1124   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1125   cell $not $2
1126     parameter \A_SIGNED 1'0
1127     parameter \A_WIDTH 4'1000
1128     parameter \Y_WIDTH 4'1000
1129     connect \A \r
1130     connect \Y $1
1131   end
1132   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1133   wire width 8 $3
1134   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1135   cell $and $4
1136     parameter \A_SIGNED 1'0
1137     parameter \A_WIDTH 4'1000
1138     parameter \B_SIGNED 1'0
1139     parameter \B_WIDTH 4'1000
1140     parameter \Y_WIDTH 4'1000
1141     connect \A \q_int
1142     connect \B $1
1143     connect \Y $3
1144   end
1145   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1146   wire width 8 $5
1147   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1148   cell $or $6
1149     parameter \A_SIGNED 1'0
1150     parameter \A_WIDTH 4'1000
1151     parameter \B_SIGNED 1'0
1152     parameter \B_WIDTH 4'1000
1153     parameter \Y_WIDTH 4'1000
1154     connect \A $3
1155     connect \B \s
1156     connect \Y $5
1157   end
1158   process $group_0
1159     assign \q_int$next \q_int
1160     assign \q_int$next $5
1161     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1162     switch \rst
1163       case 1'1
1164         assign \q_int$next 8'00000000
1165     end
1166     sync init
1167       update \q_int 8'00000000
1168     sync posedge \clk
1169       update \q_int \q_int$next
1170   end
1171   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1172   wire width 8 \q
1173   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1174   wire width 8 $7
1175   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1176   cell $not $8
1177     parameter \A_SIGNED 1'0
1178     parameter \A_WIDTH 4'1000
1179     parameter \Y_WIDTH 4'1000
1180     connect \A \r
1181     connect \Y $7
1182   end
1183   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1184   wire width 8 $9
1185   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1186   cell $and $10
1187     parameter \A_SIGNED 1'0
1188     parameter \A_WIDTH 4'1000
1189     parameter \B_SIGNED 1'0
1190     parameter \B_WIDTH 4'1000
1191     parameter \Y_WIDTH 4'1000
1192     connect \A \q_int
1193     connect \B $7
1194     connect \Y $9
1195   end
1196   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1197   wire width 8 $11
1198   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1199   cell $or $12
1200     parameter \A_SIGNED 1'0
1201     parameter \A_WIDTH 4'1000
1202     parameter \B_SIGNED 1'0
1203     parameter \B_WIDTH 4'1000
1204     parameter \Y_WIDTH 4'1000
1205     connect \A $9
1206     connect \B \s
1207     connect \Y $11
1208   end
1209   process $group_1
1210     assign \q 8'00000000
1211     assign \q $11
1212     sync init
1213   end
1214   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1215   wire width 8 $13
1216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1217   cell $not $14
1218     parameter \A_SIGNED 1'0
1219     parameter \A_WIDTH 4'1000
1220     parameter \Y_WIDTH 4'1000
1221     connect \A \q
1222     connect \Y $13
1223   end
1224   process $group_2
1225     assign \qn 8'00000000
1226     assign \qn $13
1227     sync init
1228   end
1229   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1230   wire width 8 \qlq
1231   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1232   wire width 8 $15
1233   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1234   cell $or $16
1235     parameter \A_SIGNED 1'0
1236     parameter \A_WIDTH 4'1000
1237     parameter \B_SIGNED 1'0
1238     parameter \B_WIDTH 4'1000
1239     parameter \Y_WIDTH 4'1000
1240     connect \A \q
1241     connect \B \q_int
1242     connect \Y $15
1243   end
1244   process $group_3
1245     assign \qlq 8'00000000
1246     assign \qlq $15
1247     sync init
1248   end
1249 end
1250 attribute \generator "nMigen"
1251 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.raw_l"
1252 module \raw_l$4
1253   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1254   wire width 1 input 0 \rst
1255   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1256   wire width 1 input 1 \clk
1257   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1258   wire width 8 input 2 \s
1259   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1260   wire width 8 input 3 \r
1261   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1262   wire width 8 output 4 \qn
1263   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1264   wire width 8 \q_int
1265   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1266   wire width 8 \q_int$next
1267   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1268   wire width 8 $1
1269   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1270   cell $not $2
1271     parameter \A_SIGNED 1'0
1272     parameter \A_WIDTH 4'1000
1273     parameter \Y_WIDTH 4'1000
1274     connect \A \r
1275     connect \Y $1
1276   end
1277   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1278   wire width 8 $3
1279   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1280   cell $and $4
1281     parameter \A_SIGNED 1'0
1282     parameter \A_WIDTH 4'1000
1283     parameter \B_SIGNED 1'0
1284     parameter \B_WIDTH 4'1000
1285     parameter \Y_WIDTH 4'1000
1286     connect \A \q_int
1287     connect \B $1
1288     connect \Y $3
1289   end
1290   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1291   wire width 8 $5
1292   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1293   cell $or $6
1294     parameter \A_SIGNED 1'0
1295     parameter \A_WIDTH 4'1000
1296     parameter \B_SIGNED 1'0
1297     parameter \B_WIDTH 4'1000
1298     parameter \Y_WIDTH 4'1000
1299     connect \A $3
1300     connect \B \s
1301     connect \Y $5
1302   end
1303   process $group_0
1304     assign \q_int$next \q_int
1305     assign \q_int$next $5
1306     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1307     switch \rst
1308       case 1'1
1309         assign \q_int$next 8'00000000
1310     end
1311     sync init
1312       update \q_int 8'00000000
1313     sync posedge \clk
1314       update \q_int \q_int$next
1315   end
1316   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1317   wire width 8 \q
1318   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1319   wire width 8 $7
1320   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1321   cell $not $8
1322     parameter \A_SIGNED 1'0
1323     parameter \A_WIDTH 4'1000
1324     parameter \Y_WIDTH 4'1000
1325     connect \A \r
1326     connect \Y $7
1327   end
1328   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1329   wire width 8 $9
1330   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1331   cell $and $10
1332     parameter \A_SIGNED 1'0
1333     parameter \A_WIDTH 4'1000
1334     parameter \B_SIGNED 1'0
1335     parameter \B_WIDTH 4'1000
1336     parameter \Y_WIDTH 4'1000
1337     connect \A \q_int
1338     connect \B $7
1339     connect \Y $9
1340   end
1341   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1342   wire width 8 $11
1343   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1344   cell $or $12
1345     parameter \A_SIGNED 1'0
1346     parameter \A_WIDTH 4'1000
1347     parameter \B_SIGNED 1'0
1348     parameter \B_WIDTH 4'1000
1349     parameter \Y_WIDTH 4'1000
1350     connect \A $9
1351     connect \B \s
1352     connect \Y $11
1353   end
1354   process $group_1
1355     assign \q 8'00000000
1356     assign \q $11
1357     sync init
1358   end
1359   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1360   wire width 8 $13
1361   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1362   cell $not $14
1363     parameter \A_SIGNED 1'0
1364     parameter \A_WIDTH 4'1000
1365     parameter \Y_WIDTH 4'1000
1366     connect \A \q
1367     connect \Y $13
1368   end
1369   process $group_2
1370     assign \qn 8'00000000
1371     assign \qn $13
1372     sync init
1373   end
1374   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1375   wire width 8 \qlq
1376   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1377   wire width 8 $15
1378   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1379   cell $or $16
1380     parameter \A_SIGNED 1'0
1381     parameter \A_WIDTH 4'1000
1382     parameter \B_SIGNED 1'0
1383     parameter \B_WIDTH 4'1000
1384     parameter \Y_WIDTH 4'1000
1385     connect \A \q
1386     connect \B \q_int
1387     connect \Y $15
1388   end
1389   process $group_3
1390     assign \qlq 8'00000000
1391     assign \qlq $15
1392     sync init
1393   end
1394 end
1395 attribute \generator "nMigen"
1396 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2"
1397 module \dm_fu2
1398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
1399   wire width 8 input 0 \load_hit_i
1400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
1401   wire width 8 input 1 \stwd_hit_i
1402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
1403   wire width 8 input 2 \load_v_i
1404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
1405   wire width 8 input 3 \stor_v_i
1406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
1407   wire width 1 input 4 \issue_i
1408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
1409   wire width 1 input 5 \go_die_i
1410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
1411   wire width 1 output 6 \ld_hold_st_o
1412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
1413   wire width 1 output 7 \st_hold_ld_o
1414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
1415   wire width 1 input 8 \load_h_i
1416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
1417   wire width 1 input 9 \stor_h_i
1418   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1419   wire width 1 input 10 \rst
1420   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1421   wire width 1 input 11 \clk
1422   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1423   wire width 8 \war_l_s
1424   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1425   wire width 8 \war_l_r
1426   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1427   wire width 8 \war_l_qn
1428   cell \war_l$3 \war_l
1429     connect \rst \rst
1430     connect \clk \clk
1431     connect \s \war_l_s
1432     connect \r \war_l_r
1433     connect \qn \war_l_qn
1434   end
1435   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1436   wire width 8 \raw_l_s
1437   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1438   wire width 8 \raw_l_r
1439   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1440   wire width 8 \raw_l_qn
1441   cell \raw_l$4 \raw_l
1442     connect \rst \rst
1443     connect \clk \clk
1444     connect \s \raw_l_s
1445     connect \r \raw_l_r
1446     connect \qn \raw_l_qn
1447   end
1448   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
1449   wire width 1 \i_s
1450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1451   wire width 8 $1
1452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1453   wire width 8 $2
1454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1455   cell $and $3
1456     parameter \A_SIGNED 1'0
1457     parameter \A_WIDTH 4'1000
1458     parameter \B_SIGNED 1'0
1459     parameter \B_WIDTH 1'1
1460     parameter \Y_WIDTH 4'1000
1461     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
1462     connect \B \stor_h_i
1463     connect \Y $2
1464   end
1465   connect $1 $2
1466   process $group_0
1467     assign \i_s 1'0
1468     assign \i_s $1 [0]
1469     sync init
1470   end
1471   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
1472   wire width 8 \i_s_l
1473   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
1474   wire width 8 $4
1475   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
1476   cell $and $5
1477     parameter \A_SIGNED 1'0
1478     parameter \A_WIDTH 4'1000
1479     parameter \B_SIGNED 1'0
1480     parameter \B_WIDTH 4'1000
1481     parameter \Y_WIDTH 4'1000
1482     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
1483     connect \B \load_v_i
1484     connect \Y $4
1485   end
1486   process $group_1
1487     assign \i_s_l 8'00000000
1488     assign \i_s_l $4
1489     sync init
1490   end
1491   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
1492   wire width 1 \i_l
1493   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1494   wire width 8 $6
1495   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1496   wire width 8 $7
1497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1498   cell $and $8
1499     parameter \A_SIGNED 1'0
1500     parameter \A_WIDTH 4'1000
1501     parameter \B_SIGNED 1'0
1502     parameter \B_WIDTH 1'1
1503     parameter \Y_WIDTH 4'1000
1504     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
1505     connect \B \load_h_i
1506     connect \Y $7
1507   end
1508   connect $6 $7
1509   process $group_2
1510     assign \i_l 1'0
1511     assign \i_l $6 [0]
1512     sync init
1513   end
1514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
1515   wire width 8 \i_l_s
1516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
1517   wire width 8 $9
1518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
1519   cell $and $10
1520     parameter \A_SIGNED 1'0
1521     parameter \A_WIDTH 4'1000
1522     parameter \B_SIGNED 1'0
1523     parameter \B_WIDTH 4'1000
1524     parameter \Y_WIDTH 4'1000
1525     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
1526     connect \B \stor_v_i
1527     connect \Y $9
1528   end
1529   process $group_3
1530     assign \i_l_s 8'00000000
1531     assign \i_l_s $9
1532     sync init
1533   end
1534   process $group_4
1535     assign \war_l_s 8'00000000
1536     assign \war_l_s \i_s_l
1537     sync init
1538   end
1539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1540   wire width 8 $11
1541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1542   cell $not $12
1543     parameter \A_SIGNED 1'0
1544     parameter \A_WIDTH 4'1000
1545     parameter \Y_WIDTH 4'1000
1546     connect \A \load_v_i
1547     connect \Y $11
1548   end
1549   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1550   wire width 8 $13
1551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1552   cell $or $14
1553     parameter \A_SIGNED 1'0
1554     parameter \A_WIDTH 4'1000
1555     parameter \B_SIGNED 1'0
1556     parameter \B_WIDTH 4'1000
1557     parameter \Y_WIDTH 4'1000
1558     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1559     connect \B $11
1560     connect \Y $13
1561   end
1562   process $group_5
1563     assign \war_l_r 8'11111111
1564     assign \war_l_r $13
1565     sync init
1566   end
1567   process $group_6
1568     assign \raw_l_s 8'00000000
1569     assign \raw_l_s \i_s_l
1570     sync init
1571   end
1572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1573   wire width 8 $15
1574   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1575   cell $not $16
1576     parameter \A_SIGNED 1'0
1577     parameter \A_WIDTH 4'1000
1578     parameter \Y_WIDTH 4'1000
1579     connect \A \stor_v_i
1580     connect \Y $15
1581   end
1582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1583   wire width 8 $17
1584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1585   cell $or $18
1586     parameter \A_SIGNED 1'0
1587     parameter \A_WIDTH 4'1000
1588     parameter \B_SIGNED 1'0
1589     parameter \B_WIDTH 4'1000
1590     parameter \Y_WIDTH 4'1000
1591     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1592     connect \B $15
1593     connect \Y $17
1594   end
1595   process $group_7
1596     assign \raw_l_r 8'11111111
1597     assign \raw_l_r $17
1598     sync init
1599   end
1600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1601   wire width 1 $19
1602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1603   wire width 8 $20
1604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1605   cell $and $21
1606     parameter \A_SIGNED 1'0
1607     parameter \A_WIDTH 4'1000
1608     parameter \B_SIGNED 1'0
1609     parameter \B_WIDTH 4'1000
1610     parameter \Y_WIDTH 4'1000
1611     connect \A \war_l_qn
1612     connect \B \load_hit_i
1613     connect \Y $20
1614   end
1615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1616   cell $reduce_bool $22
1617     parameter \A_SIGNED 1'0
1618     parameter \A_WIDTH 4'1000
1619     parameter \Y_WIDTH 1'1
1620     connect \A $20
1621     connect \Y $19
1622   end
1623   process $group_8
1624     assign \ld_hold_st_o 1'0
1625     assign \ld_hold_st_o $19
1626     sync init
1627   end
1628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1629   wire width 1 $23
1630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1631   wire width 8 $24
1632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1633   cell $and $25
1634     parameter \A_SIGNED 1'0
1635     parameter \A_WIDTH 4'1000
1636     parameter \B_SIGNED 1'0
1637     parameter \B_WIDTH 4'1000
1638     parameter \Y_WIDTH 4'1000
1639     connect \A \raw_l_qn
1640     connect \B \stwd_hit_i
1641     connect \Y $24
1642   end
1643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1644   cell $reduce_bool $26
1645     parameter \A_SIGNED 1'0
1646     parameter \A_WIDTH 4'1000
1647     parameter \Y_WIDTH 1'1
1648     connect \A $24
1649     connect \Y $23
1650   end
1651   process $group_9
1652     assign \st_hold_ld_o 1'0
1653     assign \st_hold_ld_o $23
1654     sync init
1655   end
1656 end
1657 attribute \generator "nMigen"
1658 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.war_l"
1659 module \war_l$5
1660   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1661   wire width 1 input 0 \rst
1662   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1663   wire width 1 input 1 \clk
1664   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1665   wire width 8 input 2 \s
1666   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1667   wire width 8 input 3 \r
1668   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1669   wire width 8 output 4 \qn
1670   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1671   wire width 8 \q_int
1672   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1673   wire width 8 \q_int$next
1674   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1675   wire width 8 $1
1676   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1677   cell $not $2
1678     parameter \A_SIGNED 1'0
1679     parameter \A_WIDTH 4'1000
1680     parameter \Y_WIDTH 4'1000
1681     connect \A \r
1682     connect \Y $1
1683   end
1684   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1685   wire width 8 $3
1686   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1687   cell $and $4
1688     parameter \A_SIGNED 1'0
1689     parameter \A_WIDTH 4'1000
1690     parameter \B_SIGNED 1'0
1691     parameter \B_WIDTH 4'1000
1692     parameter \Y_WIDTH 4'1000
1693     connect \A \q_int
1694     connect \B $1
1695     connect \Y $3
1696   end
1697   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1698   wire width 8 $5
1699   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1700   cell $or $6
1701     parameter \A_SIGNED 1'0
1702     parameter \A_WIDTH 4'1000
1703     parameter \B_SIGNED 1'0
1704     parameter \B_WIDTH 4'1000
1705     parameter \Y_WIDTH 4'1000
1706     connect \A $3
1707     connect \B \s
1708     connect \Y $5
1709   end
1710   process $group_0
1711     assign \q_int$next \q_int
1712     assign \q_int$next $5
1713     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1714     switch \rst
1715       case 1'1
1716         assign \q_int$next 8'00000000
1717     end
1718     sync init
1719       update \q_int 8'00000000
1720     sync posedge \clk
1721       update \q_int \q_int$next
1722   end
1723   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1724   wire width 8 \q
1725   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1726   wire width 8 $7
1727   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1728   cell $not $8
1729     parameter \A_SIGNED 1'0
1730     parameter \A_WIDTH 4'1000
1731     parameter \Y_WIDTH 4'1000
1732     connect \A \r
1733     connect \Y $7
1734   end
1735   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1736   wire width 8 $9
1737   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1738   cell $and $10
1739     parameter \A_SIGNED 1'0
1740     parameter \A_WIDTH 4'1000
1741     parameter \B_SIGNED 1'0
1742     parameter \B_WIDTH 4'1000
1743     parameter \Y_WIDTH 4'1000
1744     connect \A \q_int
1745     connect \B $7
1746     connect \Y $9
1747   end
1748   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1749   wire width 8 $11
1750   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1751   cell $or $12
1752     parameter \A_SIGNED 1'0
1753     parameter \A_WIDTH 4'1000
1754     parameter \B_SIGNED 1'0
1755     parameter \B_WIDTH 4'1000
1756     parameter \Y_WIDTH 4'1000
1757     connect \A $9
1758     connect \B \s
1759     connect \Y $11
1760   end
1761   process $group_1
1762     assign \q 8'00000000
1763     assign \q $11
1764     sync init
1765   end
1766   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1767   wire width 8 $13
1768   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1769   cell $not $14
1770     parameter \A_SIGNED 1'0
1771     parameter \A_WIDTH 4'1000
1772     parameter \Y_WIDTH 4'1000
1773     connect \A \q
1774     connect \Y $13
1775   end
1776   process $group_2
1777     assign \qn 8'00000000
1778     assign \qn $13
1779     sync init
1780   end
1781   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1782   wire width 8 \qlq
1783   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1784   wire width 8 $15
1785   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1786   cell $or $16
1787     parameter \A_SIGNED 1'0
1788     parameter \A_WIDTH 4'1000
1789     parameter \B_SIGNED 1'0
1790     parameter \B_WIDTH 4'1000
1791     parameter \Y_WIDTH 4'1000
1792     connect \A \q
1793     connect \B \q_int
1794     connect \Y $15
1795   end
1796   process $group_3
1797     assign \qlq 8'00000000
1798     assign \qlq $15
1799     sync init
1800   end
1801 end
1802 attribute \generator "nMigen"
1803 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.raw_l"
1804 module \raw_l$6
1805   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1806   wire width 1 input 0 \rst
1807   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1808   wire width 1 input 1 \clk
1809   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1810   wire width 8 input 2 \s
1811   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1812   wire width 8 input 3 \r
1813   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1814   wire width 8 output 4 \qn
1815   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1816   wire width 8 \q_int
1817   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1818   wire width 8 \q_int$next
1819   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1820   wire width 8 $1
1821   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1822   cell $not $2
1823     parameter \A_SIGNED 1'0
1824     parameter \A_WIDTH 4'1000
1825     parameter \Y_WIDTH 4'1000
1826     connect \A \r
1827     connect \Y $1
1828   end
1829   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1830   wire width 8 $3
1831   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1832   cell $and $4
1833     parameter \A_SIGNED 1'0
1834     parameter \A_WIDTH 4'1000
1835     parameter \B_SIGNED 1'0
1836     parameter \B_WIDTH 4'1000
1837     parameter \Y_WIDTH 4'1000
1838     connect \A \q_int
1839     connect \B $1
1840     connect \Y $3
1841   end
1842   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1843   wire width 8 $5
1844   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1845   cell $or $6
1846     parameter \A_SIGNED 1'0
1847     parameter \A_WIDTH 4'1000
1848     parameter \B_SIGNED 1'0
1849     parameter \B_WIDTH 4'1000
1850     parameter \Y_WIDTH 4'1000
1851     connect \A $3
1852     connect \B \s
1853     connect \Y $5
1854   end
1855   process $group_0
1856     assign \q_int$next \q_int
1857     assign \q_int$next $5
1858     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1859     switch \rst
1860       case 1'1
1861         assign \q_int$next 8'00000000
1862     end
1863     sync init
1864       update \q_int 8'00000000
1865     sync posedge \clk
1866       update \q_int \q_int$next
1867   end
1868   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1869   wire width 8 \q
1870   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1871   wire width 8 $7
1872   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1873   cell $not $8
1874     parameter \A_SIGNED 1'0
1875     parameter \A_WIDTH 4'1000
1876     parameter \Y_WIDTH 4'1000
1877     connect \A \r
1878     connect \Y $7
1879   end
1880   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1881   wire width 8 $9
1882   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1883   cell $and $10
1884     parameter \A_SIGNED 1'0
1885     parameter \A_WIDTH 4'1000
1886     parameter \B_SIGNED 1'0
1887     parameter \B_WIDTH 4'1000
1888     parameter \Y_WIDTH 4'1000
1889     connect \A \q_int
1890     connect \B $7
1891     connect \Y $9
1892   end
1893   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1894   wire width 8 $11
1895   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1896   cell $or $12
1897     parameter \A_SIGNED 1'0
1898     parameter \A_WIDTH 4'1000
1899     parameter \B_SIGNED 1'0
1900     parameter \B_WIDTH 4'1000
1901     parameter \Y_WIDTH 4'1000
1902     connect \A $9
1903     connect \B \s
1904     connect \Y $11
1905   end
1906   process $group_1
1907     assign \q 8'00000000
1908     assign \q $11
1909     sync init
1910   end
1911   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1912   wire width 8 $13
1913   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1914   cell $not $14
1915     parameter \A_SIGNED 1'0
1916     parameter \A_WIDTH 4'1000
1917     parameter \Y_WIDTH 4'1000
1918     connect \A \q
1919     connect \Y $13
1920   end
1921   process $group_2
1922     assign \qn 8'00000000
1923     assign \qn $13
1924     sync init
1925   end
1926   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1927   wire width 8 \qlq
1928   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1929   wire width 8 $15
1930   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1931   cell $or $16
1932     parameter \A_SIGNED 1'0
1933     parameter \A_WIDTH 4'1000
1934     parameter \B_SIGNED 1'0
1935     parameter \B_WIDTH 4'1000
1936     parameter \Y_WIDTH 4'1000
1937     connect \A \q
1938     connect \B \q_int
1939     connect \Y $15
1940   end
1941   process $group_3
1942     assign \qlq 8'00000000
1943     assign \qlq $15
1944     sync init
1945   end
1946 end
1947 attribute \generator "nMigen"
1948 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3"
1949 module \dm_fu3
1950   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
1951   wire width 8 input 0 \load_hit_i
1952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
1953   wire width 8 input 1 \stwd_hit_i
1954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
1955   wire width 8 input 2 \load_v_i
1956   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
1957   wire width 8 input 3 \stor_v_i
1958   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
1959   wire width 1 input 4 \issue_i
1960   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
1961   wire width 1 input 5 \go_die_i
1962   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
1963   wire width 1 output 6 \ld_hold_st_o
1964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
1965   wire width 1 output 7 \st_hold_ld_o
1966   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
1967   wire width 1 input 8 \load_h_i
1968   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
1969   wire width 1 input 9 \stor_h_i
1970   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1971   wire width 1 input 10 \rst
1972   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1973   wire width 1 input 11 \clk
1974   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1975   wire width 8 \war_l_s
1976   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1977   wire width 8 \war_l_r
1978   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1979   wire width 8 \war_l_qn
1980   cell \war_l$5 \war_l
1981     connect \rst \rst
1982     connect \clk \clk
1983     connect \s \war_l_s
1984     connect \r \war_l_r
1985     connect \qn \war_l_qn
1986   end
1987   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1988   wire width 8 \raw_l_s
1989   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1990   wire width 8 \raw_l_r
1991   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1992   wire width 8 \raw_l_qn
1993   cell \raw_l$6 \raw_l
1994     connect \rst \rst
1995     connect \clk \clk
1996     connect \s \raw_l_s
1997     connect \r \raw_l_r
1998     connect \qn \raw_l_qn
1999   end
2000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
2001   wire width 1 \i_s
2002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2003   wire width 8 $1
2004   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2005   wire width 8 $2
2006   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2007   cell $and $3
2008     parameter \A_SIGNED 1'0
2009     parameter \A_WIDTH 4'1000
2010     parameter \B_SIGNED 1'0
2011     parameter \B_WIDTH 1'1
2012     parameter \Y_WIDTH 4'1000
2013     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2014     connect \B \stor_h_i
2015     connect \Y $2
2016   end
2017   connect $1 $2
2018   process $group_0
2019     assign \i_s 1'0
2020     assign \i_s $1 [0]
2021     sync init
2022   end
2023   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
2024   wire width 8 \i_s_l
2025   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2026   wire width 8 $4
2027   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2028   cell $and $5
2029     parameter \A_SIGNED 1'0
2030     parameter \A_WIDTH 4'1000
2031     parameter \B_SIGNED 1'0
2032     parameter \B_WIDTH 4'1000
2033     parameter \Y_WIDTH 4'1000
2034     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
2035     connect \B \load_v_i
2036     connect \Y $4
2037   end
2038   process $group_1
2039     assign \i_s_l 8'00000000
2040     assign \i_s_l $4
2041     sync init
2042   end
2043   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
2044   wire width 1 \i_l
2045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2046   wire width 8 $6
2047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2048   wire width 8 $7
2049   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2050   cell $and $8
2051     parameter \A_SIGNED 1'0
2052     parameter \A_WIDTH 4'1000
2053     parameter \B_SIGNED 1'0
2054     parameter \B_WIDTH 1'1
2055     parameter \Y_WIDTH 4'1000
2056     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2057     connect \B \load_h_i
2058     connect \Y $7
2059   end
2060   connect $6 $7
2061   process $group_2
2062     assign \i_l 1'0
2063     assign \i_l $6 [0]
2064     sync init
2065   end
2066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
2067   wire width 8 \i_l_s
2068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2069   wire width 8 $9
2070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2071   cell $and $10
2072     parameter \A_SIGNED 1'0
2073     parameter \A_WIDTH 4'1000
2074     parameter \B_SIGNED 1'0
2075     parameter \B_WIDTH 4'1000
2076     parameter \Y_WIDTH 4'1000
2077     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
2078     connect \B \stor_v_i
2079     connect \Y $9
2080   end
2081   process $group_3
2082     assign \i_l_s 8'00000000
2083     assign \i_l_s $9
2084     sync init
2085   end
2086   process $group_4
2087     assign \war_l_s 8'00000000
2088     assign \war_l_s \i_s_l
2089     sync init
2090   end
2091   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2092   wire width 8 $11
2093   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2094   cell $not $12
2095     parameter \A_SIGNED 1'0
2096     parameter \A_WIDTH 4'1000
2097     parameter \Y_WIDTH 4'1000
2098     connect \A \load_v_i
2099     connect \Y $11
2100   end
2101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2102   wire width 8 $13
2103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2104   cell $or $14
2105     parameter \A_SIGNED 1'0
2106     parameter \A_WIDTH 4'1000
2107     parameter \B_SIGNED 1'0
2108     parameter \B_WIDTH 4'1000
2109     parameter \Y_WIDTH 4'1000
2110     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2111     connect \B $11
2112     connect \Y $13
2113   end
2114   process $group_5
2115     assign \war_l_r 8'11111111
2116     assign \war_l_r $13
2117     sync init
2118   end
2119   process $group_6
2120     assign \raw_l_s 8'00000000
2121     assign \raw_l_s \i_s_l
2122     sync init
2123   end
2124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2125   wire width 8 $15
2126   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2127   cell $not $16
2128     parameter \A_SIGNED 1'0
2129     parameter \A_WIDTH 4'1000
2130     parameter \Y_WIDTH 4'1000
2131     connect \A \stor_v_i
2132     connect \Y $15
2133   end
2134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2135   wire width 8 $17
2136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2137   cell $or $18
2138     parameter \A_SIGNED 1'0
2139     parameter \A_WIDTH 4'1000
2140     parameter \B_SIGNED 1'0
2141     parameter \B_WIDTH 4'1000
2142     parameter \Y_WIDTH 4'1000
2143     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2144     connect \B $15
2145     connect \Y $17
2146   end
2147   process $group_7
2148     assign \raw_l_r 8'11111111
2149     assign \raw_l_r $17
2150     sync init
2151   end
2152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2153   wire width 1 $19
2154   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2155   wire width 8 $20
2156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2157   cell $and $21
2158     parameter \A_SIGNED 1'0
2159     parameter \A_WIDTH 4'1000
2160     parameter \B_SIGNED 1'0
2161     parameter \B_WIDTH 4'1000
2162     parameter \Y_WIDTH 4'1000
2163     connect \A \war_l_qn
2164     connect \B \load_hit_i
2165     connect \Y $20
2166   end
2167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2168   cell $reduce_bool $22
2169     parameter \A_SIGNED 1'0
2170     parameter \A_WIDTH 4'1000
2171     parameter \Y_WIDTH 1'1
2172     connect \A $20
2173     connect \Y $19
2174   end
2175   process $group_8
2176     assign \ld_hold_st_o 1'0
2177     assign \ld_hold_st_o $19
2178     sync init
2179   end
2180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2181   wire width 1 $23
2182   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2183   wire width 8 $24
2184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2185   cell $and $25
2186     parameter \A_SIGNED 1'0
2187     parameter \A_WIDTH 4'1000
2188     parameter \B_SIGNED 1'0
2189     parameter \B_WIDTH 4'1000
2190     parameter \Y_WIDTH 4'1000
2191     connect \A \raw_l_qn
2192     connect \B \stwd_hit_i
2193     connect \Y $24
2194   end
2195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2196   cell $reduce_bool $26
2197     parameter \A_SIGNED 1'0
2198     parameter \A_WIDTH 4'1000
2199     parameter \Y_WIDTH 1'1
2200     connect \A $24
2201     connect \Y $23
2202   end
2203   process $group_9
2204     assign \st_hold_ld_o 1'0
2205     assign \st_hold_ld_o $23
2206     sync init
2207   end
2208 end
2209 attribute \generator "nMigen"
2210 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.war_l"
2211 module \war_l$7
2212   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2213   wire width 1 input 0 \rst
2214   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2215   wire width 1 input 1 \clk
2216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2217   wire width 8 input 2 \s
2218   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2219   wire width 8 input 3 \r
2220   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2221   wire width 8 output 4 \qn
2222   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2223   wire width 8 \q_int
2224   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2225   wire width 8 \q_int$next
2226   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2227   wire width 8 $1
2228   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2229   cell $not $2
2230     parameter \A_SIGNED 1'0
2231     parameter \A_WIDTH 4'1000
2232     parameter \Y_WIDTH 4'1000
2233     connect \A \r
2234     connect \Y $1
2235   end
2236   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2237   wire width 8 $3
2238   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2239   cell $and $4
2240     parameter \A_SIGNED 1'0
2241     parameter \A_WIDTH 4'1000
2242     parameter \B_SIGNED 1'0
2243     parameter \B_WIDTH 4'1000
2244     parameter \Y_WIDTH 4'1000
2245     connect \A \q_int
2246     connect \B $1
2247     connect \Y $3
2248   end
2249   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2250   wire width 8 $5
2251   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2252   cell $or $6
2253     parameter \A_SIGNED 1'0
2254     parameter \A_WIDTH 4'1000
2255     parameter \B_SIGNED 1'0
2256     parameter \B_WIDTH 4'1000
2257     parameter \Y_WIDTH 4'1000
2258     connect \A $3
2259     connect \B \s
2260     connect \Y $5
2261   end
2262   process $group_0
2263     assign \q_int$next \q_int
2264     assign \q_int$next $5
2265     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2266     switch \rst
2267       case 1'1
2268         assign \q_int$next 8'00000000
2269     end
2270     sync init
2271       update \q_int 8'00000000
2272     sync posedge \clk
2273       update \q_int \q_int$next
2274   end
2275   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2276   wire width 8 \q
2277   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2278   wire width 8 $7
2279   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2280   cell $not $8
2281     parameter \A_SIGNED 1'0
2282     parameter \A_WIDTH 4'1000
2283     parameter \Y_WIDTH 4'1000
2284     connect \A \r
2285     connect \Y $7
2286   end
2287   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2288   wire width 8 $9
2289   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2290   cell $and $10
2291     parameter \A_SIGNED 1'0
2292     parameter \A_WIDTH 4'1000
2293     parameter \B_SIGNED 1'0
2294     parameter \B_WIDTH 4'1000
2295     parameter \Y_WIDTH 4'1000
2296     connect \A \q_int
2297     connect \B $7
2298     connect \Y $9
2299   end
2300   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2301   wire width 8 $11
2302   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2303   cell $or $12
2304     parameter \A_SIGNED 1'0
2305     parameter \A_WIDTH 4'1000
2306     parameter \B_SIGNED 1'0
2307     parameter \B_WIDTH 4'1000
2308     parameter \Y_WIDTH 4'1000
2309     connect \A $9
2310     connect \B \s
2311     connect \Y $11
2312   end
2313   process $group_1
2314     assign \q 8'00000000
2315     assign \q $11
2316     sync init
2317   end
2318   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2319   wire width 8 $13
2320   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2321   cell $not $14
2322     parameter \A_SIGNED 1'0
2323     parameter \A_WIDTH 4'1000
2324     parameter \Y_WIDTH 4'1000
2325     connect \A \q
2326     connect \Y $13
2327   end
2328   process $group_2
2329     assign \qn 8'00000000
2330     assign \qn $13
2331     sync init
2332   end
2333   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2334   wire width 8 \qlq
2335   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2336   wire width 8 $15
2337   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2338   cell $or $16
2339     parameter \A_SIGNED 1'0
2340     parameter \A_WIDTH 4'1000
2341     parameter \B_SIGNED 1'0
2342     parameter \B_WIDTH 4'1000
2343     parameter \Y_WIDTH 4'1000
2344     connect \A \q
2345     connect \B \q_int
2346     connect \Y $15
2347   end
2348   process $group_3
2349     assign \qlq 8'00000000
2350     assign \qlq $15
2351     sync init
2352   end
2353 end
2354 attribute \generator "nMigen"
2355 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.raw_l"
2356 module \raw_l$8
2357   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2358   wire width 1 input 0 \rst
2359   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2360   wire width 1 input 1 \clk
2361   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2362   wire width 8 input 2 \s
2363   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2364   wire width 8 input 3 \r
2365   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2366   wire width 8 output 4 \qn
2367   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2368   wire width 8 \q_int
2369   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2370   wire width 8 \q_int$next
2371   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2372   wire width 8 $1
2373   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2374   cell $not $2
2375     parameter \A_SIGNED 1'0
2376     parameter \A_WIDTH 4'1000
2377     parameter \Y_WIDTH 4'1000
2378     connect \A \r
2379     connect \Y $1
2380   end
2381   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2382   wire width 8 $3
2383   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2384   cell $and $4
2385     parameter \A_SIGNED 1'0
2386     parameter \A_WIDTH 4'1000
2387     parameter \B_SIGNED 1'0
2388     parameter \B_WIDTH 4'1000
2389     parameter \Y_WIDTH 4'1000
2390     connect \A \q_int
2391     connect \B $1
2392     connect \Y $3
2393   end
2394   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2395   wire width 8 $5
2396   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2397   cell $or $6
2398     parameter \A_SIGNED 1'0
2399     parameter \A_WIDTH 4'1000
2400     parameter \B_SIGNED 1'0
2401     parameter \B_WIDTH 4'1000
2402     parameter \Y_WIDTH 4'1000
2403     connect \A $3
2404     connect \B \s
2405     connect \Y $5
2406   end
2407   process $group_0
2408     assign \q_int$next \q_int
2409     assign \q_int$next $5
2410     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2411     switch \rst
2412       case 1'1
2413         assign \q_int$next 8'00000000
2414     end
2415     sync init
2416       update \q_int 8'00000000
2417     sync posedge \clk
2418       update \q_int \q_int$next
2419   end
2420   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2421   wire width 8 \q
2422   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2423   wire width 8 $7
2424   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2425   cell $not $8
2426     parameter \A_SIGNED 1'0
2427     parameter \A_WIDTH 4'1000
2428     parameter \Y_WIDTH 4'1000
2429     connect \A \r
2430     connect \Y $7
2431   end
2432   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2433   wire width 8 $9
2434   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2435   cell $and $10
2436     parameter \A_SIGNED 1'0
2437     parameter \A_WIDTH 4'1000
2438     parameter \B_SIGNED 1'0
2439     parameter \B_WIDTH 4'1000
2440     parameter \Y_WIDTH 4'1000
2441     connect \A \q_int
2442     connect \B $7
2443     connect \Y $9
2444   end
2445   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2446   wire width 8 $11
2447   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2448   cell $or $12
2449     parameter \A_SIGNED 1'0
2450     parameter \A_WIDTH 4'1000
2451     parameter \B_SIGNED 1'0
2452     parameter \B_WIDTH 4'1000
2453     parameter \Y_WIDTH 4'1000
2454     connect \A $9
2455     connect \B \s
2456     connect \Y $11
2457   end
2458   process $group_1
2459     assign \q 8'00000000
2460     assign \q $11
2461     sync init
2462   end
2463   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2464   wire width 8 $13
2465   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2466   cell $not $14
2467     parameter \A_SIGNED 1'0
2468     parameter \A_WIDTH 4'1000
2469     parameter \Y_WIDTH 4'1000
2470     connect \A \q
2471     connect \Y $13
2472   end
2473   process $group_2
2474     assign \qn 8'00000000
2475     assign \qn $13
2476     sync init
2477   end
2478   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2479   wire width 8 \qlq
2480   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2481   wire width 8 $15
2482   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2483   cell $or $16
2484     parameter \A_SIGNED 1'0
2485     parameter \A_WIDTH 4'1000
2486     parameter \B_SIGNED 1'0
2487     parameter \B_WIDTH 4'1000
2488     parameter \Y_WIDTH 4'1000
2489     connect \A \q
2490     connect \B \q_int
2491     connect \Y $15
2492   end
2493   process $group_3
2494     assign \qlq 8'00000000
2495     assign \qlq $15
2496     sync init
2497   end
2498 end
2499 attribute \generator "nMigen"
2500 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4"
2501 module \dm_fu4
2502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
2503   wire width 8 input 0 \load_hit_i
2504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
2505   wire width 8 input 1 \stwd_hit_i
2506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
2507   wire width 8 input 2 \load_v_i
2508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
2509   wire width 8 input 3 \stor_v_i
2510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
2511   wire width 1 input 4 \issue_i
2512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
2513   wire width 1 input 5 \go_die_i
2514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
2515   wire width 1 output 6 \ld_hold_st_o
2516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
2517   wire width 1 output 7 \st_hold_ld_o
2518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
2519   wire width 1 input 8 \load_h_i
2520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
2521   wire width 1 input 9 \stor_h_i
2522   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2523   wire width 1 input 10 \rst
2524   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2525   wire width 1 input 11 \clk
2526   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2527   wire width 8 \war_l_s
2528   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2529   wire width 8 \war_l_r
2530   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2531   wire width 8 \war_l_qn
2532   cell \war_l$7 \war_l
2533     connect \rst \rst
2534     connect \clk \clk
2535     connect \s \war_l_s
2536     connect \r \war_l_r
2537     connect \qn \war_l_qn
2538   end
2539   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2540   wire width 8 \raw_l_s
2541   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2542   wire width 8 \raw_l_r
2543   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2544   wire width 8 \raw_l_qn
2545   cell \raw_l$8 \raw_l
2546     connect \rst \rst
2547     connect \clk \clk
2548     connect \s \raw_l_s
2549     connect \r \raw_l_r
2550     connect \qn \raw_l_qn
2551   end
2552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
2553   wire width 1 \i_s
2554   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2555   wire width 8 $1
2556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2557   wire width 8 $2
2558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2559   cell $and $3
2560     parameter \A_SIGNED 1'0
2561     parameter \A_WIDTH 4'1000
2562     parameter \B_SIGNED 1'0
2563     parameter \B_WIDTH 1'1
2564     parameter \Y_WIDTH 4'1000
2565     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2566     connect \B \stor_h_i
2567     connect \Y $2
2568   end
2569   connect $1 $2
2570   process $group_0
2571     assign \i_s 1'0
2572     assign \i_s $1 [0]
2573     sync init
2574   end
2575   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
2576   wire width 8 \i_s_l
2577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2578   wire width 8 $4
2579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2580   cell $and $5
2581     parameter \A_SIGNED 1'0
2582     parameter \A_WIDTH 4'1000
2583     parameter \B_SIGNED 1'0
2584     parameter \B_WIDTH 4'1000
2585     parameter \Y_WIDTH 4'1000
2586     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
2587     connect \B \load_v_i
2588     connect \Y $4
2589   end
2590   process $group_1
2591     assign \i_s_l 8'00000000
2592     assign \i_s_l $4
2593     sync init
2594   end
2595   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
2596   wire width 1 \i_l
2597   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2598   wire width 8 $6
2599   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2600   wire width 8 $7
2601   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2602   cell $and $8
2603     parameter \A_SIGNED 1'0
2604     parameter \A_WIDTH 4'1000
2605     parameter \B_SIGNED 1'0
2606     parameter \B_WIDTH 1'1
2607     parameter \Y_WIDTH 4'1000
2608     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2609     connect \B \load_h_i
2610     connect \Y $7
2611   end
2612   connect $6 $7
2613   process $group_2
2614     assign \i_l 1'0
2615     assign \i_l $6 [0]
2616     sync init
2617   end
2618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
2619   wire width 8 \i_l_s
2620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2621   wire width 8 $9
2622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2623   cell $and $10
2624     parameter \A_SIGNED 1'0
2625     parameter \A_WIDTH 4'1000
2626     parameter \B_SIGNED 1'0
2627     parameter \B_WIDTH 4'1000
2628     parameter \Y_WIDTH 4'1000
2629     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
2630     connect \B \stor_v_i
2631     connect \Y $9
2632   end
2633   process $group_3
2634     assign \i_l_s 8'00000000
2635     assign \i_l_s $9
2636     sync init
2637   end
2638   process $group_4
2639     assign \war_l_s 8'00000000
2640     assign \war_l_s \i_s_l
2641     sync init
2642   end
2643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2644   wire width 8 $11
2645   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2646   cell $not $12
2647     parameter \A_SIGNED 1'0
2648     parameter \A_WIDTH 4'1000
2649     parameter \Y_WIDTH 4'1000
2650     connect \A \load_v_i
2651     connect \Y $11
2652   end
2653   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2654   wire width 8 $13
2655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2656   cell $or $14
2657     parameter \A_SIGNED 1'0
2658     parameter \A_WIDTH 4'1000
2659     parameter \B_SIGNED 1'0
2660     parameter \B_WIDTH 4'1000
2661     parameter \Y_WIDTH 4'1000
2662     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2663     connect \B $11
2664     connect \Y $13
2665   end
2666   process $group_5
2667     assign \war_l_r 8'11111111
2668     assign \war_l_r $13
2669     sync init
2670   end
2671   process $group_6
2672     assign \raw_l_s 8'00000000
2673     assign \raw_l_s \i_s_l
2674     sync init
2675   end
2676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2677   wire width 8 $15
2678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2679   cell $not $16
2680     parameter \A_SIGNED 1'0
2681     parameter \A_WIDTH 4'1000
2682     parameter \Y_WIDTH 4'1000
2683     connect \A \stor_v_i
2684     connect \Y $15
2685   end
2686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2687   wire width 8 $17
2688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2689   cell $or $18
2690     parameter \A_SIGNED 1'0
2691     parameter \A_WIDTH 4'1000
2692     parameter \B_SIGNED 1'0
2693     parameter \B_WIDTH 4'1000
2694     parameter \Y_WIDTH 4'1000
2695     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2696     connect \B $15
2697     connect \Y $17
2698   end
2699   process $group_7
2700     assign \raw_l_r 8'11111111
2701     assign \raw_l_r $17
2702     sync init
2703   end
2704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2705   wire width 1 $19
2706   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2707   wire width 8 $20
2708   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2709   cell $and $21
2710     parameter \A_SIGNED 1'0
2711     parameter \A_WIDTH 4'1000
2712     parameter \B_SIGNED 1'0
2713     parameter \B_WIDTH 4'1000
2714     parameter \Y_WIDTH 4'1000
2715     connect \A \war_l_qn
2716     connect \B \load_hit_i
2717     connect \Y $20
2718   end
2719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2720   cell $reduce_bool $22
2721     parameter \A_SIGNED 1'0
2722     parameter \A_WIDTH 4'1000
2723     parameter \Y_WIDTH 1'1
2724     connect \A $20
2725     connect \Y $19
2726   end
2727   process $group_8
2728     assign \ld_hold_st_o 1'0
2729     assign \ld_hold_st_o $19
2730     sync init
2731   end
2732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2733   wire width 1 $23
2734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2735   wire width 8 $24
2736   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2737   cell $and $25
2738     parameter \A_SIGNED 1'0
2739     parameter \A_WIDTH 4'1000
2740     parameter \B_SIGNED 1'0
2741     parameter \B_WIDTH 4'1000
2742     parameter \Y_WIDTH 4'1000
2743     connect \A \raw_l_qn
2744     connect \B \stwd_hit_i
2745     connect \Y $24
2746   end
2747   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2748   cell $reduce_bool $26
2749     parameter \A_SIGNED 1'0
2750     parameter \A_WIDTH 4'1000
2751     parameter \Y_WIDTH 1'1
2752     connect \A $24
2753     connect \Y $23
2754   end
2755   process $group_9
2756     assign \st_hold_ld_o 1'0
2757     assign \st_hold_ld_o $23
2758     sync init
2759   end
2760 end
2761 attribute \generator "nMigen"
2762 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.war_l"
2763 module \war_l$9
2764   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2765   wire width 1 input 0 \rst
2766   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2767   wire width 1 input 1 \clk
2768   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2769   wire width 8 input 2 \s
2770   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2771   wire width 8 input 3 \r
2772   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2773   wire width 8 output 4 \qn
2774   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2775   wire width 8 \q_int
2776   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2777   wire width 8 \q_int$next
2778   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2779   wire width 8 $1
2780   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2781   cell $not $2
2782     parameter \A_SIGNED 1'0
2783     parameter \A_WIDTH 4'1000
2784     parameter \Y_WIDTH 4'1000
2785     connect \A \r
2786     connect \Y $1
2787   end
2788   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2789   wire width 8 $3
2790   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2791   cell $and $4
2792     parameter \A_SIGNED 1'0
2793     parameter \A_WIDTH 4'1000
2794     parameter \B_SIGNED 1'0
2795     parameter \B_WIDTH 4'1000
2796     parameter \Y_WIDTH 4'1000
2797     connect \A \q_int
2798     connect \B $1
2799     connect \Y $3
2800   end
2801   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2802   wire width 8 $5
2803   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2804   cell $or $6
2805     parameter \A_SIGNED 1'0
2806     parameter \A_WIDTH 4'1000
2807     parameter \B_SIGNED 1'0
2808     parameter \B_WIDTH 4'1000
2809     parameter \Y_WIDTH 4'1000
2810     connect \A $3
2811     connect \B \s
2812     connect \Y $5
2813   end
2814   process $group_0
2815     assign \q_int$next \q_int
2816     assign \q_int$next $5
2817     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2818     switch \rst
2819       case 1'1
2820         assign \q_int$next 8'00000000
2821     end
2822     sync init
2823       update \q_int 8'00000000
2824     sync posedge \clk
2825       update \q_int \q_int$next
2826   end
2827   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2828   wire width 8 \q
2829   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2830   wire width 8 $7
2831   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2832   cell $not $8
2833     parameter \A_SIGNED 1'0
2834     parameter \A_WIDTH 4'1000
2835     parameter \Y_WIDTH 4'1000
2836     connect \A \r
2837     connect \Y $7
2838   end
2839   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2840   wire width 8 $9
2841   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2842   cell $and $10
2843     parameter \A_SIGNED 1'0
2844     parameter \A_WIDTH 4'1000
2845     parameter \B_SIGNED 1'0
2846     parameter \B_WIDTH 4'1000
2847     parameter \Y_WIDTH 4'1000
2848     connect \A \q_int
2849     connect \B $7
2850     connect \Y $9
2851   end
2852   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2853   wire width 8 $11
2854   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2855   cell $or $12
2856     parameter \A_SIGNED 1'0
2857     parameter \A_WIDTH 4'1000
2858     parameter \B_SIGNED 1'0
2859     parameter \B_WIDTH 4'1000
2860     parameter \Y_WIDTH 4'1000
2861     connect \A $9
2862     connect \B \s
2863     connect \Y $11
2864   end
2865   process $group_1
2866     assign \q 8'00000000
2867     assign \q $11
2868     sync init
2869   end
2870   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2871   wire width 8 $13
2872   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2873   cell $not $14
2874     parameter \A_SIGNED 1'0
2875     parameter \A_WIDTH 4'1000
2876     parameter \Y_WIDTH 4'1000
2877     connect \A \q
2878     connect \Y $13
2879   end
2880   process $group_2
2881     assign \qn 8'00000000
2882     assign \qn $13
2883     sync init
2884   end
2885   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2886   wire width 8 \qlq
2887   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2888   wire width 8 $15
2889   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2890   cell $or $16
2891     parameter \A_SIGNED 1'0
2892     parameter \A_WIDTH 4'1000
2893     parameter \B_SIGNED 1'0
2894     parameter \B_WIDTH 4'1000
2895     parameter \Y_WIDTH 4'1000
2896     connect \A \q
2897     connect \B \q_int
2898     connect \Y $15
2899   end
2900   process $group_3
2901     assign \qlq 8'00000000
2902     assign \qlq $15
2903     sync init
2904   end
2905 end
2906 attribute \generator "nMigen"
2907 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.raw_l"
2908 module \raw_l$10
2909   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2910   wire width 1 input 0 \rst
2911   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2912   wire width 1 input 1 \clk
2913   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2914   wire width 8 input 2 \s
2915   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2916   wire width 8 input 3 \r
2917   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2918   wire width 8 output 4 \qn
2919   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2920   wire width 8 \q_int
2921   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2922   wire width 8 \q_int$next
2923   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2924   wire width 8 $1
2925   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2926   cell $not $2
2927     parameter \A_SIGNED 1'0
2928     parameter \A_WIDTH 4'1000
2929     parameter \Y_WIDTH 4'1000
2930     connect \A \r
2931     connect \Y $1
2932   end
2933   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2934   wire width 8 $3
2935   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2936   cell $and $4
2937     parameter \A_SIGNED 1'0
2938     parameter \A_WIDTH 4'1000
2939     parameter \B_SIGNED 1'0
2940     parameter \B_WIDTH 4'1000
2941     parameter \Y_WIDTH 4'1000
2942     connect \A \q_int
2943     connect \B $1
2944     connect \Y $3
2945   end
2946   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2947   wire width 8 $5
2948   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2949   cell $or $6
2950     parameter \A_SIGNED 1'0
2951     parameter \A_WIDTH 4'1000
2952     parameter \B_SIGNED 1'0
2953     parameter \B_WIDTH 4'1000
2954     parameter \Y_WIDTH 4'1000
2955     connect \A $3
2956     connect \B \s
2957     connect \Y $5
2958   end
2959   process $group_0
2960     assign \q_int$next \q_int
2961     assign \q_int$next $5
2962     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2963     switch \rst
2964       case 1'1
2965         assign \q_int$next 8'00000000
2966     end
2967     sync init
2968       update \q_int 8'00000000
2969     sync posedge \clk
2970       update \q_int \q_int$next
2971   end
2972   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2973   wire width 8 \q
2974   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2975   wire width 8 $7
2976   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2977   cell $not $8
2978     parameter \A_SIGNED 1'0
2979     parameter \A_WIDTH 4'1000
2980     parameter \Y_WIDTH 4'1000
2981     connect \A \r
2982     connect \Y $7
2983   end
2984   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2985   wire width 8 $9
2986   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2987   cell $and $10
2988     parameter \A_SIGNED 1'0
2989     parameter \A_WIDTH 4'1000
2990     parameter \B_SIGNED 1'0
2991     parameter \B_WIDTH 4'1000
2992     parameter \Y_WIDTH 4'1000
2993     connect \A \q_int
2994     connect \B $7
2995     connect \Y $9
2996   end
2997   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2998   wire width 8 $11
2999   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3000   cell $or $12
3001     parameter \A_SIGNED 1'0
3002     parameter \A_WIDTH 4'1000
3003     parameter \B_SIGNED 1'0
3004     parameter \B_WIDTH 4'1000
3005     parameter \Y_WIDTH 4'1000
3006     connect \A $9
3007     connect \B \s
3008     connect \Y $11
3009   end
3010   process $group_1
3011     assign \q 8'00000000
3012     assign \q $11
3013     sync init
3014   end
3015   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3016   wire width 8 $13
3017   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3018   cell $not $14
3019     parameter \A_SIGNED 1'0
3020     parameter \A_WIDTH 4'1000
3021     parameter \Y_WIDTH 4'1000
3022     connect \A \q
3023     connect \Y $13
3024   end
3025   process $group_2
3026     assign \qn 8'00000000
3027     assign \qn $13
3028     sync init
3029   end
3030   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3031   wire width 8 \qlq
3032   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3033   wire width 8 $15
3034   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3035   cell $or $16
3036     parameter \A_SIGNED 1'0
3037     parameter \A_WIDTH 4'1000
3038     parameter \B_SIGNED 1'0
3039     parameter \B_WIDTH 4'1000
3040     parameter \Y_WIDTH 4'1000
3041     connect \A \q
3042     connect \B \q_int
3043     connect \Y $15
3044   end
3045   process $group_3
3046     assign \qlq 8'00000000
3047     assign \qlq $15
3048     sync init
3049   end
3050 end
3051 attribute \generator "nMigen"
3052 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5"
3053 module \dm_fu5
3054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
3055   wire width 8 input 0 \load_hit_i
3056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
3057   wire width 8 input 1 \stwd_hit_i
3058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
3059   wire width 8 input 2 \load_v_i
3060   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
3061   wire width 8 input 3 \stor_v_i
3062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
3063   wire width 1 input 4 \issue_i
3064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
3065   wire width 1 input 5 \go_die_i
3066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
3067   wire width 1 output 6 \ld_hold_st_o
3068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
3069   wire width 1 output 7 \st_hold_ld_o
3070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
3071   wire width 1 input 8 \load_h_i
3072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
3073   wire width 1 input 9 \stor_h_i
3074   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3075   wire width 1 input 10 \rst
3076   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3077   wire width 1 input 11 \clk
3078   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3079   wire width 8 \war_l_s
3080   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3081   wire width 8 \war_l_r
3082   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3083   wire width 8 \war_l_qn
3084   cell \war_l$9 \war_l
3085     connect \rst \rst
3086     connect \clk \clk
3087     connect \s \war_l_s
3088     connect \r \war_l_r
3089     connect \qn \war_l_qn
3090   end
3091   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3092   wire width 8 \raw_l_s
3093   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3094   wire width 8 \raw_l_r
3095   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3096   wire width 8 \raw_l_qn
3097   cell \raw_l$10 \raw_l
3098     connect \rst \rst
3099     connect \clk \clk
3100     connect \s \raw_l_s
3101     connect \r \raw_l_r
3102     connect \qn \raw_l_qn
3103   end
3104   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
3105   wire width 1 \i_s
3106   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3107   wire width 8 $1
3108   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3109   wire width 8 $2
3110   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3111   cell $and $3
3112     parameter \A_SIGNED 1'0
3113     parameter \A_WIDTH 4'1000
3114     parameter \B_SIGNED 1'0
3115     parameter \B_WIDTH 1'1
3116     parameter \Y_WIDTH 4'1000
3117     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3118     connect \B \stor_h_i
3119     connect \Y $2
3120   end
3121   connect $1 $2
3122   process $group_0
3123     assign \i_s 1'0
3124     assign \i_s $1 [0]
3125     sync init
3126   end
3127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
3128   wire width 8 \i_s_l
3129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3130   wire width 8 $4
3131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3132   cell $and $5
3133     parameter \A_SIGNED 1'0
3134     parameter \A_WIDTH 4'1000
3135     parameter \B_SIGNED 1'0
3136     parameter \B_WIDTH 4'1000
3137     parameter \Y_WIDTH 4'1000
3138     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
3139     connect \B \load_v_i
3140     connect \Y $4
3141   end
3142   process $group_1
3143     assign \i_s_l 8'00000000
3144     assign \i_s_l $4
3145     sync init
3146   end
3147   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
3148   wire width 1 \i_l
3149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3150   wire width 8 $6
3151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3152   wire width 8 $7
3153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3154   cell $and $8
3155     parameter \A_SIGNED 1'0
3156     parameter \A_WIDTH 4'1000
3157     parameter \B_SIGNED 1'0
3158     parameter \B_WIDTH 1'1
3159     parameter \Y_WIDTH 4'1000
3160     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3161     connect \B \load_h_i
3162     connect \Y $7
3163   end
3164   connect $6 $7
3165   process $group_2
3166     assign \i_l 1'0
3167     assign \i_l $6 [0]
3168     sync init
3169   end
3170   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
3171   wire width 8 \i_l_s
3172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3173   wire width 8 $9
3174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3175   cell $and $10
3176     parameter \A_SIGNED 1'0
3177     parameter \A_WIDTH 4'1000
3178     parameter \B_SIGNED 1'0
3179     parameter \B_WIDTH 4'1000
3180     parameter \Y_WIDTH 4'1000
3181     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
3182     connect \B \stor_v_i
3183     connect \Y $9
3184   end
3185   process $group_3
3186     assign \i_l_s 8'00000000
3187     assign \i_l_s $9
3188     sync init
3189   end
3190   process $group_4
3191     assign \war_l_s 8'00000000
3192     assign \war_l_s \i_s_l
3193     sync init
3194   end
3195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3196   wire width 8 $11
3197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3198   cell $not $12
3199     parameter \A_SIGNED 1'0
3200     parameter \A_WIDTH 4'1000
3201     parameter \Y_WIDTH 4'1000
3202     connect \A \load_v_i
3203     connect \Y $11
3204   end
3205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3206   wire width 8 $13
3207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3208   cell $or $14
3209     parameter \A_SIGNED 1'0
3210     parameter \A_WIDTH 4'1000
3211     parameter \B_SIGNED 1'0
3212     parameter \B_WIDTH 4'1000
3213     parameter \Y_WIDTH 4'1000
3214     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3215     connect \B $11
3216     connect \Y $13
3217   end
3218   process $group_5
3219     assign \war_l_r 8'11111111
3220     assign \war_l_r $13
3221     sync init
3222   end
3223   process $group_6
3224     assign \raw_l_s 8'00000000
3225     assign \raw_l_s \i_s_l
3226     sync init
3227   end
3228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3229   wire width 8 $15
3230   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3231   cell $not $16
3232     parameter \A_SIGNED 1'0
3233     parameter \A_WIDTH 4'1000
3234     parameter \Y_WIDTH 4'1000
3235     connect \A \stor_v_i
3236     connect \Y $15
3237   end
3238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3239   wire width 8 $17
3240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3241   cell $or $18
3242     parameter \A_SIGNED 1'0
3243     parameter \A_WIDTH 4'1000
3244     parameter \B_SIGNED 1'0
3245     parameter \B_WIDTH 4'1000
3246     parameter \Y_WIDTH 4'1000
3247     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3248     connect \B $15
3249     connect \Y $17
3250   end
3251   process $group_7
3252     assign \raw_l_r 8'11111111
3253     assign \raw_l_r $17
3254     sync init
3255   end
3256   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3257   wire width 1 $19
3258   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3259   wire width 8 $20
3260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3261   cell $and $21
3262     parameter \A_SIGNED 1'0
3263     parameter \A_WIDTH 4'1000
3264     parameter \B_SIGNED 1'0
3265     parameter \B_WIDTH 4'1000
3266     parameter \Y_WIDTH 4'1000
3267     connect \A \war_l_qn
3268     connect \B \load_hit_i
3269     connect \Y $20
3270   end
3271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3272   cell $reduce_bool $22
3273     parameter \A_SIGNED 1'0
3274     parameter \A_WIDTH 4'1000
3275     parameter \Y_WIDTH 1'1
3276     connect \A $20
3277     connect \Y $19
3278   end
3279   process $group_8
3280     assign \ld_hold_st_o 1'0
3281     assign \ld_hold_st_o $19
3282     sync init
3283   end
3284   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3285   wire width 1 $23
3286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3287   wire width 8 $24
3288   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3289   cell $and $25
3290     parameter \A_SIGNED 1'0
3291     parameter \A_WIDTH 4'1000
3292     parameter \B_SIGNED 1'0
3293     parameter \B_WIDTH 4'1000
3294     parameter \Y_WIDTH 4'1000
3295     connect \A \raw_l_qn
3296     connect \B \stwd_hit_i
3297     connect \Y $24
3298   end
3299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3300   cell $reduce_bool $26
3301     parameter \A_SIGNED 1'0
3302     parameter \A_WIDTH 4'1000
3303     parameter \Y_WIDTH 1'1
3304     connect \A $24
3305     connect \Y $23
3306   end
3307   process $group_9
3308     assign \st_hold_ld_o 1'0
3309     assign \st_hold_ld_o $23
3310     sync init
3311   end
3312 end
3313 attribute \generator "nMigen"
3314 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.war_l"
3315 module \war_l$11
3316   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3317   wire width 1 input 0 \rst
3318   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3319   wire width 1 input 1 \clk
3320   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3321   wire width 8 input 2 \s
3322   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3323   wire width 8 input 3 \r
3324   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3325   wire width 8 output 4 \qn
3326   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3327   wire width 8 \q_int
3328   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3329   wire width 8 \q_int$next
3330   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3331   wire width 8 $1
3332   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3333   cell $not $2
3334     parameter \A_SIGNED 1'0
3335     parameter \A_WIDTH 4'1000
3336     parameter \Y_WIDTH 4'1000
3337     connect \A \r
3338     connect \Y $1
3339   end
3340   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3341   wire width 8 $3
3342   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3343   cell $and $4
3344     parameter \A_SIGNED 1'0
3345     parameter \A_WIDTH 4'1000
3346     parameter \B_SIGNED 1'0
3347     parameter \B_WIDTH 4'1000
3348     parameter \Y_WIDTH 4'1000
3349     connect \A \q_int
3350     connect \B $1
3351     connect \Y $3
3352   end
3353   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3354   wire width 8 $5
3355   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3356   cell $or $6
3357     parameter \A_SIGNED 1'0
3358     parameter \A_WIDTH 4'1000
3359     parameter \B_SIGNED 1'0
3360     parameter \B_WIDTH 4'1000
3361     parameter \Y_WIDTH 4'1000
3362     connect \A $3
3363     connect \B \s
3364     connect \Y $5
3365   end
3366   process $group_0
3367     assign \q_int$next \q_int
3368     assign \q_int$next $5
3369     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3370     switch \rst
3371       case 1'1
3372         assign \q_int$next 8'00000000
3373     end
3374     sync init
3375       update \q_int 8'00000000
3376     sync posedge \clk
3377       update \q_int \q_int$next
3378   end
3379   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3380   wire width 8 \q
3381   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3382   wire width 8 $7
3383   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3384   cell $not $8
3385     parameter \A_SIGNED 1'0
3386     parameter \A_WIDTH 4'1000
3387     parameter \Y_WIDTH 4'1000
3388     connect \A \r
3389     connect \Y $7
3390   end
3391   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3392   wire width 8 $9
3393   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3394   cell $and $10
3395     parameter \A_SIGNED 1'0
3396     parameter \A_WIDTH 4'1000
3397     parameter \B_SIGNED 1'0
3398     parameter \B_WIDTH 4'1000
3399     parameter \Y_WIDTH 4'1000
3400     connect \A \q_int
3401     connect \B $7
3402     connect \Y $9
3403   end
3404   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3405   wire width 8 $11
3406   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3407   cell $or $12
3408     parameter \A_SIGNED 1'0
3409     parameter \A_WIDTH 4'1000
3410     parameter \B_SIGNED 1'0
3411     parameter \B_WIDTH 4'1000
3412     parameter \Y_WIDTH 4'1000
3413     connect \A $9
3414     connect \B \s
3415     connect \Y $11
3416   end
3417   process $group_1
3418     assign \q 8'00000000
3419     assign \q $11
3420     sync init
3421   end
3422   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3423   wire width 8 $13
3424   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3425   cell $not $14
3426     parameter \A_SIGNED 1'0
3427     parameter \A_WIDTH 4'1000
3428     parameter \Y_WIDTH 4'1000
3429     connect \A \q
3430     connect \Y $13
3431   end
3432   process $group_2
3433     assign \qn 8'00000000
3434     assign \qn $13
3435     sync init
3436   end
3437   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3438   wire width 8 \qlq
3439   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3440   wire width 8 $15
3441   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3442   cell $or $16
3443     parameter \A_SIGNED 1'0
3444     parameter \A_WIDTH 4'1000
3445     parameter \B_SIGNED 1'0
3446     parameter \B_WIDTH 4'1000
3447     parameter \Y_WIDTH 4'1000
3448     connect \A \q
3449     connect \B \q_int
3450     connect \Y $15
3451   end
3452   process $group_3
3453     assign \qlq 8'00000000
3454     assign \qlq $15
3455     sync init
3456   end
3457 end
3458 attribute \generator "nMigen"
3459 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.raw_l"
3460 module \raw_l$12
3461   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3462   wire width 1 input 0 \rst
3463   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3464   wire width 1 input 1 \clk
3465   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3466   wire width 8 input 2 \s
3467   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3468   wire width 8 input 3 \r
3469   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3470   wire width 8 output 4 \qn
3471   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3472   wire width 8 \q_int
3473   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3474   wire width 8 \q_int$next
3475   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3476   wire width 8 $1
3477   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3478   cell $not $2
3479     parameter \A_SIGNED 1'0
3480     parameter \A_WIDTH 4'1000
3481     parameter \Y_WIDTH 4'1000
3482     connect \A \r
3483     connect \Y $1
3484   end
3485   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3486   wire width 8 $3
3487   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3488   cell $and $4
3489     parameter \A_SIGNED 1'0
3490     parameter \A_WIDTH 4'1000
3491     parameter \B_SIGNED 1'0
3492     parameter \B_WIDTH 4'1000
3493     parameter \Y_WIDTH 4'1000
3494     connect \A \q_int
3495     connect \B $1
3496     connect \Y $3
3497   end
3498   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3499   wire width 8 $5
3500   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3501   cell $or $6
3502     parameter \A_SIGNED 1'0
3503     parameter \A_WIDTH 4'1000
3504     parameter \B_SIGNED 1'0
3505     parameter \B_WIDTH 4'1000
3506     parameter \Y_WIDTH 4'1000
3507     connect \A $3
3508     connect \B \s
3509     connect \Y $5
3510   end
3511   process $group_0
3512     assign \q_int$next \q_int
3513     assign \q_int$next $5
3514     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3515     switch \rst
3516       case 1'1
3517         assign \q_int$next 8'00000000
3518     end
3519     sync init
3520       update \q_int 8'00000000
3521     sync posedge \clk
3522       update \q_int \q_int$next
3523   end
3524   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3525   wire width 8 \q
3526   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3527   wire width 8 $7
3528   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3529   cell $not $8
3530     parameter \A_SIGNED 1'0
3531     parameter \A_WIDTH 4'1000
3532     parameter \Y_WIDTH 4'1000
3533     connect \A \r
3534     connect \Y $7
3535   end
3536   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3537   wire width 8 $9
3538   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3539   cell $and $10
3540     parameter \A_SIGNED 1'0
3541     parameter \A_WIDTH 4'1000
3542     parameter \B_SIGNED 1'0
3543     parameter \B_WIDTH 4'1000
3544     parameter \Y_WIDTH 4'1000
3545     connect \A \q_int
3546     connect \B $7
3547     connect \Y $9
3548   end
3549   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3550   wire width 8 $11
3551   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3552   cell $or $12
3553     parameter \A_SIGNED 1'0
3554     parameter \A_WIDTH 4'1000
3555     parameter \B_SIGNED 1'0
3556     parameter \B_WIDTH 4'1000
3557     parameter \Y_WIDTH 4'1000
3558     connect \A $9
3559     connect \B \s
3560     connect \Y $11
3561   end
3562   process $group_1
3563     assign \q 8'00000000
3564     assign \q $11
3565     sync init
3566   end
3567   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3568   wire width 8 $13
3569   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3570   cell $not $14
3571     parameter \A_SIGNED 1'0
3572     parameter \A_WIDTH 4'1000
3573     parameter \Y_WIDTH 4'1000
3574     connect \A \q
3575     connect \Y $13
3576   end
3577   process $group_2
3578     assign \qn 8'00000000
3579     assign \qn $13
3580     sync init
3581   end
3582   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3583   wire width 8 \qlq
3584   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3585   wire width 8 $15
3586   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3587   cell $or $16
3588     parameter \A_SIGNED 1'0
3589     parameter \A_WIDTH 4'1000
3590     parameter \B_SIGNED 1'0
3591     parameter \B_WIDTH 4'1000
3592     parameter \Y_WIDTH 4'1000
3593     connect \A \q
3594     connect \B \q_int
3595     connect \Y $15
3596   end
3597   process $group_3
3598     assign \qlq 8'00000000
3599     assign \qlq $15
3600     sync init
3601   end
3602 end
3603 attribute \generator "nMigen"
3604 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6"
3605 module \dm_fu6
3606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
3607   wire width 8 input 0 \load_hit_i
3608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
3609   wire width 8 input 1 \stwd_hit_i
3610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
3611   wire width 8 input 2 \load_v_i
3612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
3613   wire width 8 input 3 \stor_v_i
3614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
3615   wire width 1 input 4 \issue_i
3616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
3617   wire width 1 input 5 \go_die_i
3618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
3619   wire width 1 output 6 \ld_hold_st_o
3620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
3621   wire width 1 output 7 \st_hold_ld_o
3622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
3623   wire width 1 input 8 \load_h_i
3624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
3625   wire width 1 input 9 \stor_h_i
3626   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3627   wire width 1 input 10 \rst
3628   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3629   wire width 1 input 11 \clk
3630   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3631   wire width 8 \war_l_s
3632   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3633   wire width 8 \war_l_r
3634   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3635   wire width 8 \war_l_qn
3636   cell \war_l$11 \war_l
3637     connect \rst \rst
3638     connect \clk \clk
3639     connect \s \war_l_s
3640     connect \r \war_l_r
3641     connect \qn \war_l_qn
3642   end
3643   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3644   wire width 8 \raw_l_s
3645   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3646   wire width 8 \raw_l_r
3647   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3648   wire width 8 \raw_l_qn
3649   cell \raw_l$12 \raw_l
3650     connect \rst \rst
3651     connect \clk \clk
3652     connect \s \raw_l_s
3653     connect \r \raw_l_r
3654     connect \qn \raw_l_qn
3655   end
3656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
3657   wire width 1 \i_s
3658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3659   wire width 8 $1
3660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3661   wire width 8 $2
3662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3663   cell $and $3
3664     parameter \A_SIGNED 1'0
3665     parameter \A_WIDTH 4'1000
3666     parameter \B_SIGNED 1'0
3667     parameter \B_WIDTH 1'1
3668     parameter \Y_WIDTH 4'1000
3669     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3670     connect \B \stor_h_i
3671     connect \Y $2
3672   end
3673   connect $1 $2
3674   process $group_0
3675     assign \i_s 1'0
3676     assign \i_s $1 [0]
3677     sync init
3678   end
3679   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
3680   wire width 8 \i_s_l
3681   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3682   wire width 8 $4
3683   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3684   cell $and $5
3685     parameter \A_SIGNED 1'0
3686     parameter \A_WIDTH 4'1000
3687     parameter \B_SIGNED 1'0
3688     parameter \B_WIDTH 4'1000
3689     parameter \Y_WIDTH 4'1000
3690     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
3691     connect \B \load_v_i
3692     connect \Y $4
3693   end
3694   process $group_1
3695     assign \i_s_l 8'00000000
3696     assign \i_s_l $4
3697     sync init
3698   end
3699   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
3700   wire width 1 \i_l
3701   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3702   wire width 8 $6
3703   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3704   wire width 8 $7
3705   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3706   cell $and $8
3707     parameter \A_SIGNED 1'0
3708     parameter \A_WIDTH 4'1000
3709     parameter \B_SIGNED 1'0
3710     parameter \B_WIDTH 1'1
3711     parameter \Y_WIDTH 4'1000
3712     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3713     connect \B \load_h_i
3714     connect \Y $7
3715   end
3716   connect $6 $7
3717   process $group_2
3718     assign \i_l 1'0
3719     assign \i_l $6 [0]
3720     sync init
3721   end
3722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
3723   wire width 8 \i_l_s
3724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3725   wire width 8 $9
3726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3727   cell $and $10
3728     parameter \A_SIGNED 1'0
3729     parameter \A_WIDTH 4'1000
3730     parameter \B_SIGNED 1'0
3731     parameter \B_WIDTH 4'1000
3732     parameter \Y_WIDTH 4'1000
3733     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
3734     connect \B \stor_v_i
3735     connect \Y $9
3736   end
3737   process $group_3
3738     assign \i_l_s 8'00000000
3739     assign \i_l_s $9
3740     sync init
3741   end
3742   process $group_4
3743     assign \war_l_s 8'00000000
3744     assign \war_l_s \i_s_l
3745     sync init
3746   end
3747   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3748   wire width 8 $11
3749   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3750   cell $not $12
3751     parameter \A_SIGNED 1'0
3752     parameter \A_WIDTH 4'1000
3753     parameter \Y_WIDTH 4'1000
3754     connect \A \load_v_i
3755     connect \Y $11
3756   end
3757   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3758   wire width 8 $13
3759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3760   cell $or $14
3761     parameter \A_SIGNED 1'0
3762     parameter \A_WIDTH 4'1000
3763     parameter \B_SIGNED 1'0
3764     parameter \B_WIDTH 4'1000
3765     parameter \Y_WIDTH 4'1000
3766     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3767     connect \B $11
3768     connect \Y $13
3769   end
3770   process $group_5
3771     assign \war_l_r 8'11111111
3772     assign \war_l_r $13
3773     sync init
3774   end
3775   process $group_6
3776     assign \raw_l_s 8'00000000
3777     assign \raw_l_s \i_s_l
3778     sync init
3779   end
3780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3781   wire width 8 $15
3782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3783   cell $not $16
3784     parameter \A_SIGNED 1'0
3785     parameter \A_WIDTH 4'1000
3786     parameter \Y_WIDTH 4'1000
3787     connect \A \stor_v_i
3788     connect \Y $15
3789   end
3790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3791   wire width 8 $17
3792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3793   cell $or $18
3794     parameter \A_SIGNED 1'0
3795     parameter \A_WIDTH 4'1000
3796     parameter \B_SIGNED 1'0
3797     parameter \B_WIDTH 4'1000
3798     parameter \Y_WIDTH 4'1000
3799     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3800     connect \B $15
3801     connect \Y $17
3802   end
3803   process $group_7
3804     assign \raw_l_r 8'11111111
3805     assign \raw_l_r $17
3806     sync init
3807   end
3808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3809   wire width 1 $19
3810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3811   wire width 8 $20
3812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3813   cell $and $21
3814     parameter \A_SIGNED 1'0
3815     parameter \A_WIDTH 4'1000
3816     parameter \B_SIGNED 1'0
3817     parameter \B_WIDTH 4'1000
3818     parameter \Y_WIDTH 4'1000
3819     connect \A \war_l_qn
3820     connect \B \load_hit_i
3821     connect \Y $20
3822   end
3823   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3824   cell $reduce_bool $22
3825     parameter \A_SIGNED 1'0
3826     parameter \A_WIDTH 4'1000
3827     parameter \Y_WIDTH 1'1
3828     connect \A $20
3829     connect \Y $19
3830   end
3831   process $group_8
3832     assign \ld_hold_st_o 1'0
3833     assign \ld_hold_st_o $19
3834     sync init
3835   end
3836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3837   wire width 1 $23
3838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3839   wire width 8 $24
3840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3841   cell $and $25
3842     parameter \A_SIGNED 1'0
3843     parameter \A_WIDTH 4'1000
3844     parameter \B_SIGNED 1'0
3845     parameter \B_WIDTH 4'1000
3846     parameter \Y_WIDTH 4'1000
3847     connect \A \raw_l_qn
3848     connect \B \stwd_hit_i
3849     connect \Y $24
3850   end
3851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3852   cell $reduce_bool $26
3853     parameter \A_SIGNED 1'0
3854     parameter \A_WIDTH 4'1000
3855     parameter \Y_WIDTH 1'1
3856     connect \A $24
3857     connect \Y $23
3858   end
3859   process $group_9
3860     assign \st_hold_ld_o 1'0
3861     assign \st_hold_ld_o $23
3862     sync init
3863   end
3864 end
3865 attribute \generator "nMigen"
3866 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.war_l"
3867 module \war_l$13
3868   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3869   wire width 1 input 0 \rst
3870   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3871   wire width 1 input 1 \clk
3872   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3873   wire width 8 input 2 \s
3874   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3875   wire width 8 input 3 \r
3876   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3877   wire width 8 output 4 \qn
3878   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3879   wire width 8 \q_int
3880   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3881   wire width 8 \q_int$next
3882   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3883   wire width 8 $1
3884   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3885   cell $not $2
3886     parameter \A_SIGNED 1'0
3887     parameter \A_WIDTH 4'1000
3888     parameter \Y_WIDTH 4'1000
3889     connect \A \r
3890     connect \Y $1
3891   end
3892   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3893   wire width 8 $3
3894   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3895   cell $and $4
3896     parameter \A_SIGNED 1'0
3897     parameter \A_WIDTH 4'1000
3898     parameter \B_SIGNED 1'0
3899     parameter \B_WIDTH 4'1000
3900     parameter \Y_WIDTH 4'1000
3901     connect \A \q_int
3902     connect \B $1
3903     connect \Y $3
3904   end
3905   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3906   wire width 8 $5
3907   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3908   cell $or $6
3909     parameter \A_SIGNED 1'0
3910     parameter \A_WIDTH 4'1000
3911     parameter \B_SIGNED 1'0
3912     parameter \B_WIDTH 4'1000
3913     parameter \Y_WIDTH 4'1000
3914     connect \A $3
3915     connect \B \s
3916     connect \Y $5
3917   end
3918   process $group_0
3919     assign \q_int$next \q_int
3920     assign \q_int$next $5
3921     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3922     switch \rst
3923       case 1'1
3924         assign \q_int$next 8'00000000
3925     end
3926     sync init
3927       update \q_int 8'00000000
3928     sync posedge \clk
3929       update \q_int \q_int$next
3930   end
3931   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3932   wire width 8 \q
3933   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3934   wire width 8 $7
3935   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3936   cell $not $8
3937     parameter \A_SIGNED 1'0
3938     parameter \A_WIDTH 4'1000
3939     parameter \Y_WIDTH 4'1000
3940     connect \A \r
3941     connect \Y $7
3942   end
3943   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3944   wire width 8 $9
3945   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3946   cell $and $10
3947     parameter \A_SIGNED 1'0
3948     parameter \A_WIDTH 4'1000
3949     parameter \B_SIGNED 1'0
3950     parameter \B_WIDTH 4'1000
3951     parameter \Y_WIDTH 4'1000
3952     connect \A \q_int
3953     connect \B $7
3954     connect \Y $9
3955   end
3956   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3957   wire width 8 $11
3958   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3959   cell $or $12
3960     parameter \A_SIGNED 1'0
3961     parameter \A_WIDTH 4'1000
3962     parameter \B_SIGNED 1'0
3963     parameter \B_WIDTH 4'1000
3964     parameter \Y_WIDTH 4'1000
3965     connect \A $9
3966     connect \B \s
3967     connect \Y $11
3968   end
3969   process $group_1
3970     assign \q 8'00000000
3971     assign \q $11
3972     sync init
3973   end
3974   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3975   wire width 8 $13
3976   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3977   cell $not $14
3978     parameter \A_SIGNED 1'0
3979     parameter \A_WIDTH 4'1000
3980     parameter \Y_WIDTH 4'1000
3981     connect \A \q
3982     connect \Y $13
3983   end
3984   process $group_2
3985     assign \qn 8'00000000
3986     assign \qn $13
3987     sync init
3988   end
3989   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3990   wire width 8 \qlq
3991   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3992   wire width 8 $15
3993   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3994   cell $or $16
3995     parameter \A_SIGNED 1'0
3996     parameter \A_WIDTH 4'1000
3997     parameter \B_SIGNED 1'0
3998     parameter \B_WIDTH 4'1000
3999     parameter \Y_WIDTH 4'1000
4000     connect \A \q
4001     connect \B \q_int
4002     connect \Y $15
4003   end
4004   process $group_3
4005     assign \qlq 8'00000000
4006     assign \qlq $15
4007     sync init
4008   end
4009 end
4010 attribute \generator "nMigen"
4011 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.raw_l"
4012 module \raw_l$14
4013   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4014   wire width 1 input 0 \rst
4015   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4016   wire width 1 input 1 \clk
4017   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4018   wire width 8 input 2 \s
4019   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4020   wire width 8 input 3 \r
4021   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4022   wire width 8 output 4 \qn
4023   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4024   wire width 8 \q_int
4025   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4026   wire width 8 \q_int$next
4027   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4028   wire width 8 $1
4029   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4030   cell $not $2
4031     parameter \A_SIGNED 1'0
4032     parameter \A_WIDTH 4'1000
4033     parameter \Y_WIDTH 4'1000
4034     connect \A \r
4035     connect \Y $1
4036   end
4037   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4038   wire width 8 $3
4039   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4040   cell $and $4
4041     parameter \A_SIGNED 1'0
4042     parameter \A_WIDTH 4'1000
4043     parameter \B_SIGNED 1'0
4044     parameter \B_WIDTH 4'1000
4045     parameter \Y_WIDTH 4'1000
4046     connect \A \q_int
4047     connect \B $1
4048     connect \Y $3
4049   end
4050   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4051   wire width 8 $5
4052   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4053   cell $or $6
4054     parameter \A_SIGNED 1'0
4055     parameter \A_WIDTH 4'1000
4056     parameter \B_SIGNED 1'0
4057     parameter \B_WIDTH 4'1000
4058     parameter \Y_WIDTH 4'1000
4059     connect \A $3
4060     connect \B \s
4061     connect \Y $5
4062   end
4063   process $group_0
4064     assign \q_int$next \q_int
4065     assign \q_int$next $5
4066     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
4067     switch \rst
4068       case 1'1
4069         assign \q_int$next 8'00000000
4070     end
4071     sync init
4072       update \q_int 8'00000000
4073     sync posedge \clk
4074       update \q_int \q_int$next
4075   end
4076   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
4077   wire width 8 \q
4078   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4079   wire width 8 $7
4080   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4081   cell $not $8
4082     parameter \A_SIGNED 1'0
4083     parameter \A_WIDTH 4'1000
4084     parameter \Y_WIDTH 4'1000
4085     connect \A \r
4086     connect \Y $7
4087   end
4088   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4089   wire width 8 $9
4090   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4091   cell $and $10
4092     parameter \A_SIGNED 1'0
4093     parameter \A_WIDTH 4'1000
4094     parameter \B_SIGNED 1'0
4095     parameter \B_WIDTH 4'1000
4096     parameter \Y_WIDTH 4'1000
4097     connect \A \q_int
4098     connect \B $7
4099     connect \Y $9
4100   end
4101   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4102   wire width 8 $11
4103   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4104   cell $or $12
4105     parameter \A_SIGNED 1'0
4106     parameter \A_WIDTH 4'1000
4107     parameter \B_SIGNED 1'0
4108     parameter \B_WIDTH 4'1000
4109     parameter \Y_WIDTH 4'1000
4110     connect \A $9
4111     connect \B \s
4112     connect \Y $11
4113   end
4114   process $group_1
4115     assign \q 8'00000000
4116     assign \q $11
4117     sync init
4118   end
4119   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
4120   wire width 8 $13
4121   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
4122   cell $not $14
4123     parameter \A_SIGNED 1'0
4124     parameter \A_WIDTH 4'1000
4125     parameter \Y_WIDTH 4'1000
4126     connect \A \q
4127     connect \Y $13
4128   end
4129   process $group_2
4130     assign \qn 8'00000000
4131     assign \qn $13
4132     sync init
4133   end
4134   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
4135   wire width 8 \qlq
4136   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
4137   wire width 8 $15
4138   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
4139   cell $or $16
4140     parameter \A_SIGNED 1'0
4141     parameter \A_WIDTH 4'1000
4142     parameter \B_SIGNED 1'0
4143     parameter \B_WIDTH 4'1000
4144     parameter \Y_WIDTH 4'1000
4145     connect \A \q
4146     connect \B \q_int
4147     connect \Y $15
4148   end
4149   process $group_3
4150     assign \qlq 8'00000000
4151     assign \qlq $15
4152     sync init
4153   end
4154 end
4155 attribute \generator "nMigen"
4156 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7"
4157 module \dm_fu7
4158   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4159   wire width 8 input 0 \load_hit_i
4160   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4161   wire width 8 input 1 \stwd_hit_i
4162   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4163   wire width 8 input 2 \load_v_i
4164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4165   wire width 8 input 3 \stor_v_i
4166   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4167   wire width 1 input 4 \issue_i
4168   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4169   wire width 1 input 5 \go_die_i
4170   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4171   wire width 1 output 6 \ld_hold_st_o
4172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4173   wire width 1 output 7 \st_hold_ld_o
4174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4175   wire width 1 input 8 \load_h_i
4176   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4177   wire width 1 input 9 \stor_h_i
4178   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4179   wire width 1 input 10 \rst
4180   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4181   wire width 1 input 11 \clk
4182   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4183   wire width 8 \war_l_s
4184   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4185   wire width 8 \war_l_r
4186   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4187   wire width 8 \war_l_qn
4188   cell \war_l$13 \war_l
4189     connect \rst \rst
4190     connect \clk \clk
4191     connect \s \war_l_s
4192     connect \r \war_l_r
4193     connect \qn \war_l_qn
4194   end
4195   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4196   wire width 8 \raw_l_s
4197   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4198   wire width 8 \raw_l_r
4199   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4200   wire width 8 \raw_l_qn
4201   cell \raw_l$14 \raw_l
4202     connect \rst \rst
4203     connect \clk \clk
4204     connect \s \raw_l_s
4205     connect \r \raw_l_r
4206     connect \qn \raw_l_qn
4207   end
4208   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
4209   wire width 1 \i_s
4210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4211   wire width 8 $1
4212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4213   wire width 8 $2
4214   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4215   cell $and $3
4216     parameter \A_SIGNED 1'0
4217     parameter \A_WIDTH 4'1000
4218     parameter \B_SIGNED 1'0
4219     parameter \B_WIDTH 1'1
4220     parameter \Y_WIDTH 4'1000
4221     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
4222     connect \B \stor_h_i
4223     connect \Y $2
4224   end
4225   connect $1 $2
4226   process $group_0
4227     assign \i_s 1'0
4228     assign \i_s $1 [0]
4229     sync init
4230   end
4231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
4232   wire width 8 \i_s_l
4233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
4234   wire width 8 $4
4235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
4236   cell $and $5
4237     parameter \A_SIGNED 1'0
4238     parameter \A_WIDTH 4'1000
4239     parameter \B_SIGNED 1'0
4240     parameter \B_WIDTH 4'1000
4241     parameter \Y_WIDTH 4'1000
4242     connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
4243     connect \B \load_v_i
4244     connect \Y $4
4245   end
4246   process $group_1
4247     assign \i_s_l 8'00000000
4248     assign \i_s_l $4
4249     sync init
4250   end
4251   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
4252   wire width 1 \i_l
4253   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4254   wire width 8 $6
4255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4256   wire width 8 $7
4257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4258   cell $and $8
4259     parameter \A_SIGNED 1'0
4260     parameter \A_WIDTH 4'1000
4261     parameter \B_SIGNED 1'0
4262     parameter \B_WIDTH 1'1
4263     parameter \Y_WIDTH 4'1000
4264     connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
4265     connect \B \load_h_i
4266     connect \Y $7
4267   end
4268   connect $6 $7
4269   process $group_2
4270     assign \i_l 1'0
4271     assign \i_l $6 [0]
4272     sync init
4273   end
4274   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
4275   wire width 8 \i_l_s
4276   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
4277   wire width 8 $9
4278   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
4279   cell $and $10
4280     parameter \A_SIGNED 1'0
4281     parameter \A_WIDTH 4'1000
4282     parameter \B_SIGNED 1'0
4283     parameter \B_WIDTH 4'1000
4284     parameter \Y_WIDTH 4'1000
4285     connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
4286     connect \B \stor_v_i
4287     connect \Y $9
4288   end
4289   process $group_3
4290     assign \i_l_s 8'00000000
4291     assign \i_l_s $9
4292     sync init
4293   end
4294   process $group_4
4295     assign \war_l_s 8'00000000
4296     assign \war_l_s \i_s_l
4297     sync init
4298   end
4299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4300   wire width 8 $11
4301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4302   cell $not $12
4303     parameter \A_SIGNED 1'0
4304     parameter \A_WIDTH 4'1000
4305     parameter \Y_WIDTH 4'1000
4306     connect \A \load_v_i
4307     connect \Y $11
4308   end
4309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4310   wire width 8 $13
4311   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4312   cell $or $14
4313     parameter \A_SIGNED 1'0
4314     parameter \A_WIDTH 4'1000
4315     parameter \B_SIGNED 1'0
4316     parameter \B_WIDTH 4'1000
4317     parameter \Y_WIDTH 4'1000
4318     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
4319     connect \B $11
4320     connect \Y $13
4321   end
4322   process $group_5
4323     assign \war_l_r 8'11111111
4324     assign \war_l_r $13
4325     sync init
4326   end
4327   process $group_6
4328     assign \raw_l_s 8'00000000
4329     assign \raw_l_s \i_s_l
4330     sync init
4331   end
4332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4333   wire width 8 $15
4334   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4335   cell $not $16
4336     parameter \A_SIGNED 1'0
4337     parameter \A_WIDTH 4'1000
4338     parameter \Y_WIDTH 4'1000
4339     connect \A \stor_v_i
4340     connect \Y $15
4341   end
4342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4343   wire width 8 $17
4344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4345   cell $or $18
4346     parameter \A_SIGNED 1'0
4347     parameter \A_WIDTH 4'1000
4348     parameter \B_SIGNED 1'0
4349     parameter \B_WIDTH 4'1000
4350     parameter \Y_WIDTH 4'1000
4351     connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
4352     connect \B $15
4353     connect \Y $17
4354   end
4355   process $group_7
4356     assign \raw_l_r 8'11111111
4357     assign \raw_l_r $17
4358     sync init
4359   end
4360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4361   wire width 1 $19
4362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4363   wire width 8 $20
4364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4365   cell $and $21
4366     parameter \A_SIGNED 1'0
4367     parameter \A_WIDTH 4'1000
4368     parameter \B_SIGNED 1'0
4369     parameter \B_WIDTH 4'1000
4370     parameter \Y_WIDTH 4'1000
4371     connect \A \war_l_qn
4372     connect \B \load_hit_i
4373     connect \Y $20
4374   end
4375   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4376   cell $reduce_bool $22
4377     parameter \A_SIGNED 1'0
4378     parameter \A_WIDTH 4'1000
4379     parameter \Y_WIDTH 1'1
4380     connect \A $20
4381     connect \Y $19
4382   end
4383   process $group_8
4384     assign \ld_hold_st_o 1'0
4385     assign \ld_hold_st_o $19
4386     sync init
4387   end
4388   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4389   wire width 1 $23
4390   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4391   wire width 8 $24
4392   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4393   cell $and $25
4394     parameter \A_SIGNED 1'0
4395     parameter \A_WIDTH 4'1000
4396     parameter \B_SIGNED 1'0
4397     parameter \B_WIDTH 4'1000
4398     parameter \Y_WIDTH 4'1000
4399     connect \A \raw_l_qn
4400     connect \B \stwd_hit_i
4401     connect \Y $24
4402   end
4403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4404   cell $reduce_bool $26
4405     parameter \A_SIGNED 1'0
4406     parameter \A_WIDTH 4'1000
4407     parameter \Y_WIDTH 1'1
4408     connect \A $24
4409     connect \Y $23
4410   end
4411   process $group_9
4412     assign \st_hold_ld_o 1'0
4413     assign \st_hold_ld_o $23
4414     sync init
4415   end
4416 end
4417 attribute \generator "nMigen"
4418 attribute \nmigen.hierarchy "top.ldstdeps"
4419 module \ldstdeps
4420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
4421   wire width 8 input 0 \ld_pend_i
4422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
4423   wire width 8 input 1 \st_pend_i
4424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
4425   wire width 8 input 2 \issue_i
4426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
4427   wire width 8 input 3 \load_hit_i
4428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
4429   wire width 8 input 4 \stwd_hit_i
4430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
4431   wire width 8 input 5 \go_die_i
4432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
4433   wire width 8 output 6 \ld_hold_st_o
4434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
4435   wire width 8 output 7 \st_hold_ld_o
4436   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4437   wire width 1 input 8 \rst
4438   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4439   wire width 1 input 9 \clk
4440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4441   wire width 8 \dm_fu0_load_hit_i
4442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4443   wire width 8 \dm_fu0_stwd_hit_i
4444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4445   wire width 8 \dm_fu0_load_v_i
4446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4447   wire width 8 \dm_fu0_stor_v_i
4448   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4449   wire width 1 \dm_fu0_issue_i
4450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4451   wire width 1 \dm_fu0_go_die_i
4452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4453   wire width 1 \dm_fu0_ld_hold_st_o
4454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4455   wire width 1 \dm_fu0_st_hold_ld_o
4456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4457   wire width 1 \dm_fu0_load_h_i
4458   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4459   wire width 1 \dm_fu0_stor_h_i
4460   cell \dm_fu0 \dm_fu0
4461     connect \load_hit_i \dm_fu0_load_hit_i
4462     connect \stwd_hit_i \dm_fu0_stwd_hit_i
4463     connect \load_v_i \dm_fu0_load_v_i
4464     connect \stor_v_i \dm_fu0_stor_v_i
4465     connect \issue_i \dm_fu0_issue_i
4466     connect \go_die_i \dm_fu0_go_die_i
4467     connect \ld_hold_st_o \dm_fu0_ld_hold_st_o
4468     connect \st_hold_ld_o \dm_fu0_st_hold_ld_o
4469     connect \load_h_i \dm_fu0_load_h_i
4470     connect \stor_h_i \dm_fu0_stor_h_i
4471     connect \rst \rst
4472     connect \clk \clk
4473   end
4474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4475   wire width 8 \dm_fu1_load_hit_i
4476   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4477   wire width 8 \dm_fu1_stwd_hit_i
4478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4479   wire width 8 \dm_fu1_load_v_i
4480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4481   wire width 8 \dm_fu1_stor_v_i
4482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4483   wire width 1 \dm_fu1_issue_i
4484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4485   wire width 1 \dm_fu1_go_die_i
4486   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4487   wire width 1 \dm_fu1_ld_hold_st_o
4488   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4489   wire width 1 \dm_fu1_st_hold_ld_o
4490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4491   wire width 1 \dm_fu1_load_h_i
4492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4493   wire width 1 \dm_fu1_stor_h_i
4494   cell \dm_fu1 \dm_fu1
4495     connect \load_hit_i \dm_fu1_load_hit_i
4496     connect \stwd_hit_i \dm_fu1_stwd_hit_i
4497     connect \load_v_i \dm_fu1_load_v_i
4498     connect \stor_v_i \dm_fu1_stor_v_i
4499     connect \issue_i \dm_fu1_issue_i
4500     connect \go_die_i \dm_fu1_go_die_i
4501     connect \ld_hold_st_o \dm_fu1_ld_hold_st_o
4502     connect \st_hold_ld_o \dm_fu1_st_hold_ld_o
4503     connect \load_h_i \dm_fu1_load_h_i
4504     connect \stor_h_i \dm_fu1_stor_h_i
4505     connect \rst \rst
4506     connect \clk \clk
4507   end
4508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4509   wire width 8 \dm_fu2_load_hit_i
4510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4511   wire width 8 \dm_fu2_stwd_hit_i
4512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4513   wire width 8 \dm_fu2_load_v_i
4514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4515   wire width 8 \dm_fu2_stor_v_i
4516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4517   wire width 1 \dm_fu2_issue_i
4518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4519   wire width 1 \dm_fu2_go_die_i
4520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4521   wire width 1 \dm_fu2_ld_hold_st_o
4522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4523   wire width 1 \dm_fu2_st_hold_ld_o
4524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4525   wire width 1 \dm_fu2_load_h_i
4526   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4527   wire width 1 \dm_fu2_stor_h_i
4528   cell \dm_fu2 \dm_fu2
4529     connect \load_hit_i \dm_fu2_load_hit_i
4530     connect \stwd_hit_i \dm_fu2_stwd_hit_i
4531     connect \load_v_i \dm_fu2_load_v_i
4532     connect \stor_v_i \dm_fu2_stor_v_i
4533     connect \issue_i \dm_fu2_issue_i
4534     connect \go_die_i \dm_fu2_go_die_i
4535     connect \ld_hold_st_o \dm_fu2_ld_hold_st_o
4536     connect \st_hold_ld_o \dm_fu2_st_hold_ld_o
4537     connect \load_h_i \dm_fu2_load_h_i
4538     connect \stor_h_i \dm_fu2_stor_h_i
4539     connect \rst \rst
4540     connect \clk \clk
4541   end
4542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4543   wire width 8 \dm_fu3_load_hit_i
4544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4545   wire width 8 \dm_fu3_stwd_hit_i
4546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4547   wire width 8 \dm_fu3_load_v_i
4548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4549   wire width 8 \dm_fu3_stor_v_i
4550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4551   wire width 1 \dm_fu3_issue_i
4552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4553   wire width 1 \dm_fu3_go_die_i
4554   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4555   wire width 1 \dm_fu3_ld_hold_st_o
4556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4557   wire width 1 \dm_fu3_st_hold_ld_o
4558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4559   wire width 1 \dm_fu3_load_h_i
4560   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4561   wire width 1 \dm_fu3_stor_h_i
4562   cell \dm_fu3 \dm_fu3
4563     connect \load_hit_i \dm_fu3_load_hit_i
4564     connect \stwd_hit_i \dm_fu3_stwd_hit_i
4565     connect \load_v_i \dm_fu3_load_v_i
4566     connect \stor_v_i \dm_fu3_stor_v_i
4567     connect \issue_i \dm_fu3_issue_i
4568     connect \go_die_i \dm_fu3_go_die_i
4569     connect \ld_hold_st_o \dm_fu3_ld_hold_st_o
4570     connect \st_hold_ld_o \dm_fu3_st_hold_ld_o
4571     connect \load_h_i \dm_fu3_load_h_i
4572     connect \stor_h_i \dm_fu3_stor_h_i
4573     connect \rst \rst
4574     connect \clk \clk
4575   end
4576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4577   wire width 8 \dm_fu4_load_hit_i
4578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4579   wire width 8 \dm_fu4_stwd_hit_i
4580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4581   wire width 8 \dm_fu4_load_v_i
4582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4583   wire width 8 \dm_fu4_stor_v_i
4584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4585   wire width 1 \dm_fu4_issue_i
4586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4587   wire width 1 \dm_fu4_go_die_i
4588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4589   wire width 1 \dm_fu4_ld_hold_st_o
4590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4591   wire width 1 \dm_fu4_st_hold_ld_o
4592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4593   wire width 1 \dm_fu4_load_h_i
4594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4595   wire width 1 \dm_fu4_stor_h_i
4596   cell \dm_fu4 \dm_fu4
4597     connect \load_hit_i \dm_fu4_load_hit_i
4598     connect \stwd_hit_i \dm_fu4_stwd_hit_i
4599     connect \load_v_i \dm_fu4_load_v_i
4600     connect \stor_v_i \dm_fu4_stor_v_i
4601     connect \issue_i \dm_fu4_issue_i
4602     connect \go_die_i \dm_fu4_go_die_i
4603     connect \ld_hold_st_o \dm_fu4_ld_hold_st_o
4604     connect \st_hold_ld_o \dm_fu4_st_hold_ld_o
4605     connect \load_h_i \dm_fu4_load_h_i
4606     connect \stor_h_i \dm_fu4_stor_h_i
4607     connect \rst \rst
4608     connect \clk \clk
4609   end
4610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4611   wire width 8 \dm_fu5_load_hit_i
4612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4613   wire width 8 \dm_fu5_stwd_hit_i
4614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4615   wire width 8 \dm_fu5_load_v_i
4616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4617   wire width 8 \dm_fu5_stor_v_i
4618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4619   wire width 1 \dm_fu5_issue_i
4620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4621   wire width 1 \dm_fu5_go_die_i
4622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4623   wire width 1 \dm_fu5_ld_hold_st_o
4624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4625   wire width 1 \dm_fu5_st_hold_ld_o
4626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4627   wire width 1 \dm_fu5_load_h_i
4628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4629   wire width 1 \dm_fu5_stor_h_i
4630   cell \dm_fu5 \dm_fu5
4631     connect \load_hit_i \dm_fu5_load_hit_i
4632     connect \stwd_hit_i \dm_fu5_stwd_hit_i
4633     connect \load_v_i \dm_fu5_load_v_i
4634     connect \stor_v_i \dm_fu5_stor_v_i
4635     connect \issue_i \dm_fu5_issue_i
4636     connect \go_die_i \dm_fu5_go_die_i
4637     connect \ld_hold_st_o \dm_fu5_ld_hold_st_o
4638     connect \st_hold_ld_o \dm_fu5_st_hold_ld_o
4639     connect \load_h_i \dm_fu5_load_h_i
4640     connect \stor_h_i \dm_fu5_stor_h_i
4641     connect \rst \rst
4642     connect \clk \clk
4643   end
4644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4645   wire width 8 \dm_fu6_load_hit_i
4646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4647   wire width 8 \dm_fu6_stwd_hit_i
4648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4649   wire width 8 \dm_fu6_load_v_i
4650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4651   wire width 8 \dm_fu6_stor_v_i
4652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4653   wire width 1 \dm_fu6_issue_i
4654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4655   wire width 1 \dm_fu6_go_die_i
4656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4657   wire width 1 \dm_fu6_ld_hold_st_o
4658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4659   wire width 1 \dm_fu6_st_hold_ld_o
4660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4661   wire width 1 \dm_fu6_load_h_i
4662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4663   wire width 1 \dm_fu6_stor_h_i
4664   cell \dm_fu6 \dm_fu6
4665     connect \load_hit_i \dm_fu6_load_hit_i
4666     connect \stwd_hit_i \dm_fu6_stwd_hit_i
4667     connect \load_v_i \dm_fu6_load_v_i
4668     connect \stor_v_i \dm_fu6_stor_v_i
4669     connect \issue_i \dm_fu6_issue_i
4670     connect \go_die_i \dm_fu6_go_die_i
4671     connect \ld_hold_st_o \dm_fu6_ld_hold_st_o
4672     connect \st_hold_ld_o \dm_fu6_st_hold_ld_o
4673     connect \load_h_i \dm_fu6_load_h_i
4674     connect \stor_h_i \dm_fu6_stor_h_i
4675     connect \rst \rst
4676     connect \clk \clk
4677   end
4678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4679   wire width 8 \dm_fu7_load_hit_i
4680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4681   wire width 8 \dm_fu7_stwd_hit_i
4682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4683   wire width 8 \dm_fu7_load_v_i
4684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4685   wire width 8 \dm_fu7_stor_v_i
4686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4687   wire width 1 \dm_fu7_issue_i
4688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4689   wire width 1 \dm_fu7_go_die_i
4690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4691   wire width 1 \dm_fu7_ld_hold_st_o
4692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4693   wire width 1 \dm_fu7_st_hold_ld_o
4694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4695   wire width 1 \dm_fu7_load_h_i
4696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4697   wire width 1 \dm_fu7_stor_h_i
4698   cell \dm_fu7 \dm_fu7
4699     connect \load_hit_i \dm_fu7_load_hit_i
4700     connect \stwd_hit_i \dm_fu7_stwd_hit_i
4701     connect \load_v_i \dm_fu7_load_v_i
4702     connect \stor_v_i \dm_fu7_stor_v_i
4703     connect \issue_i \dm_fu7_issue_i
4704     connect \go_die_i \dm_fu7_go_die_i
4705     connect \ld_hold_st_o \dm_fu7_ld_hold_st_o
4706     connect \st_hold_ld_o \dm_fu7_st_hold_ld_o
4707     connect \load_h_i \dm_fu7_load_h_i
4708     connect \stor_h_i \dm_fu7_stor_h_i
4709     connect \rst \rst
4710     connect \clk \clk
4711   end
4712   process $group_0
4713     assign \dm_fu0_load_hit_i 8'00000000
4714     assign \dm_fu0_load_hit_i \load_hit_i
4715     sync init
4716   end
4717   process $group_1
4718     assign \dm_fu0_stwd_hit_i 8'00000000
4719     assign \dm_fu0_stwd_hit_i \stwd_hit_i
4720     sync init
4721   end
4722   process $group_2
4723     assign \dm_fu0_load_v_i 8'00000000
4724     assign \dm_fu0_load_v_i \ld_pend_i
4725     sync init
4726   end
4727   process $group_3
4728     assign \dm_fu0_stor_v_i 8'00000000
4729     assign \dm_fu0_stor_v_i \st_pend_i
4730     sync init
4731   end
4732   process $group_4
4733     assign \dm_fu1_load_hit_i 8'00000000
4734     assign \dm_fu1_load_hit_i \load_hit_i
4735     sync init
4736   end
4737   process $group_5
4738     assign \dm_fu1_stwd_hit_i 8'00000000
4739     assign \dm_fu1_stwd_hit_i \stwd_hit_i
4740     sync init
4741   end
4742   process $group_6
4743     assign \dm_fu1_load_v_i 8'00000000
4744     assign \dm_fu1_load_v_i \ld_pend_i
4745     sync init
4746   end
4747   process $group_7
4748     assign \dm_fu1_stor_v_i 8'00000000
4749     assign \dm_fu1_stor_v_i \st_pend_i
4750     sync init
4751   end
4752   process $group_8
4753     assign \dm_fu2_load_hit_i 8'00000000
4754     assign \dm_fu2_load_hit_i \load_hit_i
4755     sync init
4756   end
4757   process $group_9
4758     assign \dm_fu2_stwd_hit_i 8'00000000
4759     assign \dm_fu2_stwd_hit_i \stwd_hit_i
4760     sync init
4761   end
4762   process $group_10
4763     assign \dm_fu2_load_v_i 8'00000000
4764     assign \dm_fu2_load_v_i \ld_pend_i
4765     sync init
4766   end
4767   process $group_11
4768     assign \dm_fu2_stor_v_i 8'00000000
4769     assign \dm_fu2_stor_v_i \st_pend_i
4770     sync init
4771   end
4772   process $group_12
4773     assign \dm_fu3_load_hit_i 8'00000000
4774     assign \dm_fu3_load_hit_i \load_hit_i
4775     sync init
4776   end
4777   process $group_13
4778     assign \dm_fu3_stwd_hit_i 8'00000000
4779     assign \dm_fu3_stwd_hit_i \stwd_hit_i
4780     sync init
4781   end
4782   process $group_14
4783     assign \dm_fu3_load_v_i 8'00000000
4784     assign \dm_fu3_load_v_i \ld_pend_i
4785     sync init
4786   end
4787   process $group_15
4788     assign \dm_fu3_stor_v_i 8'00000000
4789     assign \dm_fu3_stor_v_i \st_pend_i
4790     sync init
4791   end
4792   process $group_16
4793     assign \dm_fu4_load_hit_i 8'00000000
4794     assign \dm_fu4_load_hit_i \load_hit_i
4795     sync init
4796   end
4797   process $group_17
4798     assign \dm_fu4_stwd_hit_i 8'00000000
4799     assign \dm_fu4_stwd_hit_i \stwd_hit_i
4800     sync init
4801   end
4802   process $group_18
4803     assign \dm_fu4_load_v_i 8'00000000
4804     assign \dm_fu4_load_v_i \ld_pend_i
4805     sync init
4806   end
4807   process $group_19
4808     assign \dm_fu4_stor_v_i 8'00000000
4809     assign \dm_fu4_stor_v_i \st_pend_i
4810     sync init
4811   end
4812   process $group_20
4813     assign \dm_fu5_load_hit_i 8'00000000
4814     assign \dm_fu5_load_hit_i \load_hit_i
4815     sync init
4816   end
4817   process $group_21
4818     assign \dm_fu5_stwd_hit_i 8'00000000
4819     assign \dm_fu5_stwd_hit_i \stwd_hit_i
4820     sync init
4821   end
4822   process $group_22
4823     assign \dm_fu5_load_v_i 8'00000000
4824     assign \dm_fu5_load_v_i \ld_pend_i
4825     sync init
4826   end
4827   process $group_23
4828     assign \dm_fu5_stor_v_i 8'00000000
4829     assign \dm_fu5_stor_v_i \st_pend_i
4830     sync init
4831   end
4832   process $group_24
4833     assign \dm_fu6_load_hit_i 8'00000000
4834     assign \dm_fu6_load_hit_i \load_hit_i
4835     sync init
4836   end
4837   process $group_25
4838     assign \dm_fu6_stwd_hit_i 8'00000000
4839     assign \dm_fu6_stwd_hit_i \stwd_hit_i
4840     sync init
4841   end
4842   process $group_26
4843     assign \dm_fu6_load_v_i 8'00000000
4844     assign \dm_fu6_load_v_i \ld_pend_i
4845     sync init
4846   end
4847   process $group_27
4848     assign \dm_fu6_stor_v_i 8'00000000
4849     assign \dm_fu6_stor_v_i \st_pend_i
4850     sync init
4851   end
4852   process $group_28
4853     assign \dm_fu7_load_hit_i 8'00000000
4854     assign \dm_fu7_load_hit_i \load_hit_i
4855     sync init
4856   end
4857   process $group_29
4858     assign \dm_fu7_stwd_hit_i 8'00000000
4859     assign \dm_fu7_stwd_hit_i \stwd_hit_i
4860     sync init
4861   end
4862   process $group_30
4863     assign \dm_fu7_load_v_i 8'00000000
4864     assign \dm_fu7_load_v_i \ld_pend_i
4865     sync init
4866   end
4867   process $group_31
4868     assign \dm_fu7_stor_v_i 8'00000000
4869     assign \dm_fu7_stor_v_i \st_pend_i
4870     sync init
4871   end
4872   process $group_32
4873     assign \dm_fu0_issue_i 1'0
4874     assign \dm_fu1_issue_i 1'0
4875     assign \dm_fu2_issue_i 1'0
4876     assign \dm_fu3_issue_i 1'0
4877     assign \dm_fu4_issue_i 1'0
4878     assign \dm_fu5_issue_i 1'0
4879     assign \dm_fu6_issue_i 1'0
4880     assign \dm_fu7_issue_i 1'0
4881     assign { \dm_fu7_issue_i \dm_fu6_issue_i \dm_fu5_issue_i \dm_fu4_issue_i \dm_fu3_issue_i \dm_fu2_issue_i \dm_fu1_issue_i \dm_fu0_issue_i } \issue_i
4882     sync init
4883   end
4884   process $group_40
4885     assign \dm_fu0_go_die_i 1'0
4886     assign \dm_fu1_go_die_i 1'0
4887     assign \dm_fu2_go_die_i 1'0
4888     assign \dm_fu3_go_die_i 1'0
4889     assign \dm_fu4_go_die_i 1'0
4890     assign \dm_fu5_go_die_i 1'0
4891     assign \dm_fu6_go_die_i 1'0
4892     assign \dm_fu7_go_die_i 1'0
4893     assign { \dm_fu7_go_die_i \dm_fu6_go_die_i \dm_fu5_go_die_i \dm_fu4_go_die_i \dm_fu3_go_die_i \dm_fu2_go_die_i \dm_fu1_go_die_i \dm_fu0_go_die_i } \go_die_i
4894     sync init
4895   end
4896   process $group_48
4897     assign \ld_hold_st_o 8'00000000
4898     assign \ld_hold_st_o { \dm_fu7_ld_hold_st_o \dm_fu6_ld_hold_st_o \dm_fu5_ld_hold_st_o \dm_fu4_ld_hold_st_o \dm_fu3_ld_hold_st_o \dm_fu2_ld_hold_st_o \dm_fu1_ld_hold_st_o \dm_fu0_ld_hold_st_o }
4899     sync init
4900   end
4901   process $group_49
4902     assign \st_hold_ld_o 8'00000000
4903     assign \st_hold_ld_o { \dm_fu7_st_hold_ld_o \dm_fu6_st_hold_ld_o \dm_fu5_st_hold_ld_o \dm_fu4_st_hold_ld_o \dm_fu3_st_hold_ld_o \dm_fu2_st_hold_ld_o \dm_fu1_st_hold_ld_o \dm_fu0_st_hold_ld_o }
4904     sync init
4905   end
4906   process $group_50
4907     assign \dm_fu0_load_h_i 1'0
4908     assign \dm_fu1_load_h_i 1'0
4909     assign \dm_fu2_load_h_i 1'0
4910     assign \dm_fu3_load_h_i 1'0
4911     assign \dm_fu4_load_h_i 1'0
4912     assign \dm_fu5_load_h_i 1'0
4913     assign \dm_fu6_load_h_i 1'0
4914     assign \dm_fu7_load_h_i 1'0
4915     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4916     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4917     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4918     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4919     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4920     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4921     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4922     assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4923     sync init
4924   end
4925   process $group_58
4926     assign \dm_fu0_stor_h_i 1'0
4927     assign \dm_fu1_stor_h_i 1'0
4928     assign \dm_fu2_stor_h_i 1'0
4929     assign \dm_fu3_stor_h_i 1'0
4930     assign \dm_fu4_stor_h_i 1'0
4931     assign \dm_fu5_stor_h_i 1'0
4932     assign \dm_fu6_stor_h_i 1'0
4933     assign \dm_fu7_stor_h_i 1'0
4934     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4935     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4936     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4937     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4938     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4939     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4940     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4941     assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4942     sync init
4943   end
4944 end
4945 attribute \generator "nMigen"
4946 attribute \nmigen.hierarchy "top.fumemdeps.dm0.st_c"
4947 module \st_c
4948   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4949   wire width 1 input 0 \rst
4950   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4951   wire width 1 input 1 \clk
4952   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4953   wire width 8 input 2 \s
4954   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4955   wire width 8 input 3 \r
4956   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
4957   wire width 8 output 4 \qlq
4958   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4959   wire width 8 \q_int
4960   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4961   wire width 8 \q_int$next
4962   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4963   wire width 8 $1
4964   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4965   cell $not $2
4966     parameter \A_SIGNED 1'0
4967     parameter \A_WIDTH 4'1000
4968     parameter \Y_WIDTH 4'1000
4969     connect \A \r
4970     connect \Y $1
4971   end
4972   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4973   wire width 8 $3
4974   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4975   cell $and $4
4976     parameter \A_SIGNED 1'0
4977     parameter \A_WIDTH 4'1000
4978     parameter \B_SIGNED 1'0
4979     parameter \B_WIDTH 4'1000
4980     parameter \Y_WIDTH 4'1000
4981     connect \A \q_int
4982     connect \B $1
4983     connect \Y $3
4984   end
4985   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4986   wire width 8 $5
4987   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4988   cell $or $6
4989     parameter \A_SIGNED 1'0
4990     parameter \A_WIDTH 4'1000
4991     parameter \B_SIGNED 1'0
4992     parameter \B_WIDTH 4'1000
4993     parameter \Y_WIDTH 4'1000
4994     connect \A $3
4995     connect \B \s
4996     connect \Y $5
4997   end
4998   process $group_0
4999     assign \q_int$next \q_int
5000     assign \q_int$next $5
5001     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5002     switch \rst
5003       case 1'1
5004         assign \q_int$next 8'00000000
5005     end
5006     sync init
5007       update \q_int 8'00000000
5008     sync posedge \clk
5009       update \q_int \q_int$next
5010   end
5011   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5012   wire width 8 \q
5013   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5014   wire width 8 $7
5015   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5016   cell $not $8
5017     parameter \A_SIGNED 1'0
5018     parameter \A_WIDTH 4'1000
5019     parameter \Y_WIDTH 4'1000
5020     connect \A \r
5021     connect \Y $7
5022   end
5023   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5024   wire width 8 $9
5025   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5026   cell $and $10
5027     parameter \A_SIGNED 1'0
5028     parameter \A_WIDTH 4'1000
5029     parameter \B_SIGNED 1'0
5030     parameter \B_WIDTH 4'1000
5031     parameter \Y_WIDTH 4'1000
5032     connect \A \q_int
5033     connect \B $7
5034     connect \Y $9
5035   end
5036   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5037   wire width 8 $11
5038   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5039   cell $or $12
5040     parameter \A_SIGNED 1'0
5041     parameter \A_WIDTH 4'1000
5042     parameter \B_SIGNED 1'0
5043     parameter \B_WIDTH 4'1000
5044     parameter \Y_WIDTH 4'1000
5045     connect \A $9
5046     connect \B \s
5047     connect \Y $11
5048   end
5049   process $group_1
5050     assign \q 8'00000000
5051     assign \q $11
5052     sync init
5053   end
5054   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5055   wire width 8 \qn
5056   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5057   wire width 8 $13
5058   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5059   cell $not $14
5060     parameter \A_SIGNED 1'0
5061     parameter \A_WIDTH 4'1000
5062     parameter \Y_WIDTH 4'1000
5063     connect \A \q
5064     connect \Y $13
5065   end
5066   process $group_2
5067     assign \qn 8'00000000
5068     assign \qn $13
5069     sync init
5070   end
5071   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5072   wire width 8 $15
5073   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5074   cell $or $16
5075     parameter \A_SIGNED 1'0
5076     parameter \A_WIDTH 4'1000
5077     parameter \B_SIGNED 1'0
5078     parameter \B_WIDTH 4'1000
5079     parameter \Y_WIDTH 4'1000
5080     connect \A \q
5081     connect \B \q_int
5082     connect \Y $15
5083   end
5084   process $group_3
5085     assign \qlq 8'00000000
5086     assign \qlq $15
5087     sync init
5088   end
5089 end
5090 attribute \generator "nMigen"
5091 attribute \nmigen.hierarchy "top.fumemdeps.dm0.ld_c"
5092 module \ld_c
5093   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5094   wire width 1 input 0 \rst
5095   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5096   wire width 1 input 1 \clk
5097   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5098   wire width 8 input 2 \s
5099   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5100   wire width 8 input 3 \r
5101   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5102   wire width 8 output 4 \qlq
5103   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5104   wire width 8 \q_int
5105   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5106   wire width 8 \q_int$next
5107   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5108   wire width 8 $1
5109   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5110   cell $not $2
5111     parameter \A_SIGNED 1'0
5112     parameter \A_WIDTH 4'1000
5113     parameter \Y_WIDTH 4'1000
5114     connect \A \r
5115     connect \Y $1
5116   end
5117   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5118   wire width 8 $3
5119   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5120   cell $and $4
5121     parameter \A_SIGNED 1'0
5122     parameter \A_WIDTH 4'1000
5123     parameter \B_SIGNED 1'0
5124     parameter \B_WIDTH 4'1000
5125     parameter \Y_WIDTH 4'1000
5126     connect \A \q_int
5127     connect \B $1
5128     connect \Y $3
5129   end
5130   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5131   wire width 8 $5
5132   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5133   cell $or $6
5134     parameter \A_SIGNED 1'0
5135     parameter \A_WIDTH 4'1000
5136     parameter \B_SIGNED 1'0
5137     parameter \B_WIDTH 4'1000
5138     parameter \Y_WIDTH 4'1000
5139     connect \A $3
5140     connect \B \s
5141     connect \Y $5
5142   end
5143   process $group_0
5144     assign \q_int$next \q_int
5145     assign \q_int$next $5
5146     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5147     switch \rst
5148       case 1'1
5149         assign \q_int$next 8'00000000
5150     end
5151     sync init
5152       update \q_int 8'00000000
5153     sync posedge \clk
5154       update \q_int \q_int$next
5155   end
5156   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5157   wire width 8 \q
5158   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5159   wire width 8 $7
5160   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5161   cell $not $8
5162     parameter \A_SIGNED 1'0
5163     parameter \A_WIDTH 4'1000
5164     parameter \Y_WIDTH 4'1000
5165     connect \A \r
5166     connect \Y $7
5167   end
5168   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5169   wire width 8 $9
5170   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5171   cell $and $10
5172     parameter \A_SIGNED 1'0
5173     parameter \A_WIDTH 4'1000
5174     parameter \B_SIGNED 1'0
5175     parameter \B_WIDTH 4'1000
5176     parameter \Y_WIDTH 4'1000
5177     connect \A \q_int
5178     connect \B $7
5179     connect \Y $9
5180   end
5181   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5182   wire width 8 $11
5183   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5184   cell $or $12
5185     parameter \A_SIGNED 1'0
5186     parameter \A_WIDTH 4'1000
5187     parameter \B_SIGNED 1'0
5188     parameter \B_WIDTH 4'1000
5189     parameter \Y_WIDTH 4'1000
5190     connect \A $9
5191     connect \B \s
5192     connect \Y $11
5193   end
5194   process $group_1
5195     assign \q 8'00000000
5196     assign \q $11
5197     sync init
5198   end
5199   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5200   wire width 8 \qn
5201   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5202   wire width 8 $13
5203   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5204   cell $not $14
5205     parameter \A_SIGNED 1'0
5206     parameter \A_WIDTH 4'1000
5207     parameter \Y_WIDTH 4'1000
5208     connect \A \q
5209     connect \Y $13
5210   end
5211   process $group_2
5212     assign \qn 8'00000000
5213     assign \qn $13
5214     sync init
5215   end
5216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5217   wire width 8 $15
5218   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5219   cell $or $16
5220     parameter \A_SIGNED 1'0
5221     parameter \A_WIDTH 4'1000
5222     parameter \B_SIGNED 1'0
5223     parameter \B_WIDTH 4'1000
5224     parameter \Y_WIDTH 4'1000
5225     connect \A \q
5226     connect \B \q_int
5227     connect \Y $15
5228   end
5229   process $group_3
5230     assign \qlq 8'00000000
5231     assign \qlq $15
5232     sync init
5233   end
5234 end
5235 attribute \generator "nMigen"
5236 attribute \nmigen.hierarchy "top.fumemdeps.dm0"
5237 module \dm0
5238   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5239   wire width 1 input 0 \rst
5240   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5241   wire width 1 input 1 \clk
5242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
5243   wire width 8 output 2 \st_wait_o
5244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
5245   wire width 8 output 3 \ld_wait_o
5246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
5247   wire width 8 input 4 \issue_i
5248   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
5249   wire width 8 input 5 \go_st_i
5250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
5251   wire width 8 input 6 \go_ld_i
5252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
5253   wire width 8 input 7 \go_die_i
5254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
5255   wire width 8 input 8 \st_pend_i
5256   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
5257   wire width 8 input 9 \ld_pend_i
5258   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5259   wire width 8 \st_c_s
5260   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5261   wire width 8 \st_c_r
5262   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5263   wire width 8 \st_c_qlq
5264   cell \st_c \st_c
5265     connect \rst \rst
5266     connect \clk \clk
5267     connect \s \st_c_s
5268     connect \r \st_c_r
5269     connect \qlq \st_c_qlq
5270   end
5271   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5272   wire width 8 \ld_c_s
5273   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5274   wire width 8 \ld_c_r
5275   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5276   wire width 8 \ld_c_qlq
5277   cell \ld_c \ld_c
5278     connect \rst \rst
5279     connect \clk \clk
5280     connect \s \ld_c_s
5281     connect \r \ld_c_r
5282     connect \qlq \ld_c_qlq
5283   end
5284   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5285   wire width 8 $1
5286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5287   cell $and $2
5288     parameter \A_SIGNED 1'0
5289     parameter \A_WIDTH 4'1000
5290     parameter \B_SIGNED 1'0
5291     parameter \B_WIDTH 4'1000
5292     parameter \Y_WIDTH 4'1000
5293     connect \A \issue_i
5294     connect \B \st_pend_i
5295     connect \Y $1
5296   end
5297   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5298   wire width 9 $3
5299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5300   wire width 8 $4
5301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5302   cell $and $5
5303     parameter \A_SIGNED 1'0
5304     parameter \A_WIDTH 4'1000
5305     parameter \B_SIGNED 1'0
5306     parameter \B_WIDTH 4'1000
5307     parameter \Y_WIDTH 4'1000
5308     connect \A \issue_i
5309     connect \B \st_pend_i
5310     connect \Y $4
5311   end
5312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5313   wire width 9 $6
5314   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5315   cell $and $7
5316     parameter \A_SIGNED 1'1
5317     parameter \A_WIDTH 4'1000
5318     parameter \B_SIGNED 1'1
5319     parameter \B_WIDTH 4'1000
5320     parameter \Y_WIDTH 4'1001
5321     connect \A $4
5322     connect \B 8'11111110
5323     connect \Y $6
5324   end
5325   connect $3 $6
5326   process $group_0
5327     assign \st_c_s 8'00000000
5328     assign \st_c_s $1
5329     assign \st_c_s $3 [7:0]
5330     sync init
5331   end
5332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5333   wire width 8 $8
5334   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5335   cell $and $9
5336     parameter \A_SIGNED 1'0
5337     parameter \A_WIDTH 4'1000
5338     parameter \B_SIGNED 1'0
5339     parameter \B_WIDTH 4'1000
5340     parameter \Y_WIDTH 4'1000
5341     connect \A \issue_i
5342     connect \B \ld_pend_i
5343     connect \Y $8
5344   end
5345   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5346   wire width 9 $10
5347   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5348   wire width 8 $11
5349   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5350   cell $and $12
5351     parameter \A_SIGNED 1'0
5352     parameter \A_WIDTH 4'1000
5353     parameter \B_SIGNED 1'0
5354     parameter \B_WIDTH 4'1000
5355     parameter \Y_WIDTH 4'1000
5356     connect \A \issue_i
5357     connect \B \ld_pend_i
5358     connect \Y $11
5359   end
5360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5361   wire width 9 $13
5362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5363   cell $and $14
5364     parameter \A_SIGNED 1'1
5365     parameter \A_WIDTH 4'1000
5366     parameter \B_SIGNED 1'1
5367     parameter \B_WIDTH 4'1000
5368     parameter \Y_WIDTH 4'1001
5369     connect \A $11
5370     connect \B 8'11111110
5371     connect \Y $13
5372   end
5373   connect $10 $13
5374   process $group_1
5375     assign \ld_c_s 8'00000000
5376     assign \ld_c_s $8
5377     assign \ld_c_s $10 [7:0]
5378     sync init
5379   end
5380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5381   wire width 8 $15
5382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5383   cell $or $16
5384     parameter \A_SIGNED 1'0
5385     parameter \A_WIDTH 4'1000
5386     parameter \B_SIGNED 1'0
5387     parameter \B_WIDTH 4'1000
5388     parameter \Y_WIDTH 4'1000
5389     connect \A \go_ld_i
5390     connect \B \go_die_i
5391     connect \Y $15
5392   end
5393   process $group_2
5394     assign \ld_c_r 8'11111111
5395     assign \ld_c_r $15
5396     sync init
5397   end
5398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5399   wire width 8 $17
5400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5401   cell $or $18
5402     parameter \A_SIGNED 1'0
5403     parameter \A_WIDTH 4'1000
5404     parameter \B_SIGNED 1'0
5405     parameter \B_WIDTH 4'1000
5406     parameter \Y_WIDTH 4'1000
5407     connect \A \go_st_i
5408     connect \B \go_die_i
5409     connect \Y $17
5410   end
5411   process $group_3
5412     assign \st_c_r 8'11111111
5413     assign \st_c_r $17
5414     sync init
5415   end
5416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5417   wire width 8 $19
5418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5419   cell $not $20
5420     parameter \A_SIGNED 1'0
5421     parameter \A_WIDTH 4'1000
5422     parameter \Y_WIDTH 4'1000
5423     connect \A \issue_i
5424     connect \Y $19
5425   end
5426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5427   wire width 8 $21
5428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5429   cell $and $22
5430     parameter \A_SIGNED 1'0
5431     parameter \A_WIDTH 4'1000
5432     parameter \B_SIGNED 1'0
5433     parameter \B_WIDTH 4'1000
5434     parameter \Y_WIDTH 4'1000
5435     connect \A \st_c_qlq
5436     connect \B $19
5437     connect \Y $21
5438   end
5439   process $group_4
5440     assign \st_wait_o 8'00000000
5441     assign \st_wait_o $21
5442     sync init
5443   end
5444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5445   wire width 8 $23
5446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5447   cell $not $24
5448     parameter \A_SIGNED 1'0
5449     parameter \A_WIDTH 4'1000
5450     parameter \Y_WIDTH 4'1000
5451     connect \A \issue_i
5452     connect \Y $23
5453   end
5454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5455   wire width 8 $25
5456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5457   cell $and $26
5458     parameter \A_SIGNED 1'0
5459     parameter \A_WIDTH 4'1000
5460     parameter \B_SIGNED 1'0
5461     parameter \B_WIDTH 4'1000
5462     parameter \Y_WIDTH 4'1000
5463     connect \A \ld_c_qlq
5464     connect \B $23
5465     connect \Y $25
5466   end
5467   process $group_5
5468     assign \ld_wait_o 8'00000000
5469     assign \ld_wait_o $25
5470     sync init
5471   end
5472 end
5473 attribute \generator "nMigen"
5474 attribute \nmigen.hierarchy "top.fumemdeps.dm1.st_c"
5475 module \st_c$15
5476   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5477   wire width 1 input 0 \rst
5478   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5479   wire width 1 input 1 \clk
5480   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5481   wire width 8 input 2 \s
5482   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5483   wire width 8 input 3 \r
5484   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5485   wire width 8 output 4 \qlq
5486   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5487   wire width 8 \q_int
5488   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5489   wire width 8 \q_int$next
5490   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5491   wire width 8 $1
5492   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5493   cell $not $2
5494     parameter \A_SIGNED 1'0
5495     parameter \A_WIDTH 4'1000
5496     parameter \Y_WIDTH 4'1000
5497     connect \A \r
5498     connect \Y $1
5499   end
5500   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5501   wire width 8 $3
5502   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5503   cell $and $4
5504     parameter \A_SIGNED 1'0
5505     parameter \A_WIDTH 4'1000
5506     parameter \B_SIGNED 1'0
5507     parameter \B_WIDTH 4'1000
5508     parameter \Y_WIDTH 4'1000
5509     connect \A \q_int
5510     connect \B $1
5511     connect \Y $3
5512   end
5513   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5514   wire width 8 $5
5515   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5516   cell $or $6
5517     parameter \A_SIGNED 1'0
5518     parameter \A_WIDTH 4'1000
5519     parameter \B_SIGNED 1'0
5520     parameter \B_WIDTH 4'1000
5521     parameter \Y_WIDTH 4'1000
5522     connect \A $3
5523     connect \B \s
5524     connect \Y $5
5525   end
5526   process $group_0
5527     assign \q_int$next \q_int
5528     assign \q_int$next $5
5529     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5530     switch \rst
5531       case 1'1
5532         assign \q_int$next 8'00000000
5533     end
5534     sync init
5535       update \q_int 8'00000000
5536     sync posedge \clk
5537       update \q_int \q_int$next
5538   end
5539   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5540   wire width 8 \q
5541   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5542   wire width 8 $7
5543   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5544   cell $not $8
5545     parameter \A_SIGNED 1'0
5546     parameter \A_WIDTH 4'1000
5547     parameter \Y_WIDTH 4'1000
5548     connect \A \r
5549     connect \Y $7
5550   end
5551   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5552   wire width 8 $9
5553   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5554   cell $and $10
5555     parameter \A_SIGNED 1'0
5556     parameter \A_WIDTH 4'1000
5557     parameter \B_SIGNED 1'0
5558     parameter \B_WIDTH 4'1000
5559     parameter \Y_WIDTH 4'1000
5560     connect \A \q_int
5561     connect \B $7
5562     connect \Y $9
5563   end
5564   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5565   wire width 8 $11
5566   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5567   cell $or $12
5568     parameter \A_SIGNED 1'0
5569     parameter \A_WIDTH 4'1000
5570     parameter \B_SIGNED 1'0
5571     parameter \B_WIDTH 4'1000
5572     parameter \Y_WIDTH 4'1000
5573     connect \A $9
5574     connect \B \s
5575     connect \Y $11
5576   end
5577   process $group_1
5578     assign \q 8'00000000
5579     assign \q $11
5580     sync init
5581   end
5582   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5583   wire width 8 \qn
5584   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5585   wire width 8 $13
5586   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5587   cell $not $14
5588     parameter \A_SIGNED 1'0
5589     parameter \A_WIDTH 4'1000
5590     parameter \Y_WIDTH 4'1000
5591     connect \A \q
5592     connect \Y $13
5593   end
5594   process $group_2
5595     assign \qn 8'00000000
5596     assign \qn $13
5597     sync init
5598   end
5599   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5600   wire width 8 $15
5601   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5602   cell $or $16
5603     parameter \A_SIGNED 1'0
5604     parameter \A_WIDTH 4'1000
5605     parameter \B_SIGNED 1'0
5606     parameter \B_WIDTH 4'1000
5607     parameter \Y_WIDTH 4'1000
5608     connect \A \q
5609     connect \B \q_int
5610     connect \Y $15
5611   end
5612   process $group_3
5613     assign \qlq 8'00000000
5614     assign \qlq $15
5615     sync init
5616   end
5617 end
5618 attribute \generator "nMigen"
5619 attribute \nmigen.hierarchy "top.fumemdeps.dm1.ld_c"
5620 module \ld_c$16
5621   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5622   wire width 1 input 0 \rst
5623   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5624   wire width 1 input 1 \clk
5625   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5626   wire width 8 input 2 \s
5627   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5628   wire width 8 input 3 \r
5629   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5630   wire width 8 output 4 \qlq
5631   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5632   wire width 8 \q_int
5633   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5634   wire width 8 \q_int$next
5635   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5636   wire width 8 $1
5637   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5638   cell $not $2
5639     parameter \A_SIGNED 1'0
5640     parameter \A_WIDTH 4'1000
5641     parameter \Y_WIDTH 4'1000
5642     connect \A \r
5643     connect \Y $1
5644   end
5645   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5646   wire width 8 $3
5647   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5648   cell $and $4
5649     parameter \A_SIGNED 1'0
5650     parameter \A_WIDTH 4'1000
5651     parameter \B_SIGNED 1'0
5652     parameter \B_WIDTH 4'1000
5653     parameter \Y_WIDTH 4'1000
5654     connect \A \q_int
5655     connect \B $1
5656     connect \Y $3
5657   end
5658   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5659   wire width 8 $5
5660   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5661   cell $or $6
5662     parameter \A_SIGNED 1'0
5663     parameter \A_WIDTH 4'1000
5664     parameter \B_SIGNED 1'0
5665     parameter \B_WIDTH 4'1000
5666     parameter \Y_WIDTH 4'1000
5667     connect \A $3
5668     connect \B \s
5669     connect \Y $5
5670   end
5671   process $group_0
5672     assign \q_int$next \q_int
5673     assign \q_int$next $5
5674     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5675     switch \rst
5676       case 1'1
5677         assign \q_int$next 8'00000000
5678     end
5679     sync init
5680       update \q_int 8'00000000
5681     sync posedge \clk
5682       update \q_int \q_int$next
5683   end
5684   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5685   wire width 8 \q
5686   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5687   wire width 8 $7
5688   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5689   cell $not $8
5690     parameter \A_SIGNED 1'0
5691     parameter \A_WIDTH 4'1000
5692     parameter \Y_WIDTH 4'1000
5693     connect \A \r
5694     connect \Y $7
5695   end
5696   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5697   wire width 8 $9
5698   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5699   cell $and $10
5700     parameter \A_SIGNED 1'0
5701     parameter \A_WIDTH 4'1000
5702     parameter \B_SIGNED 1'0
5703     parameter \B_WIDTH 4'1000
5704     parameter \Y_WIDTH 4'1000
5705     connect \A \q_int
5706     connect \B $7
5707     connect \Y $9
5708   end
5709   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5710   wire width 8 $11
5711   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5712   cell $or $12
5713     parameter \A_SIGNED 1'0
5714     parameter \A_WIDTH 4'1000
5715     parameter \B_SIGNED 1'0
5716     parameter \B_WIDTH 4'1000
5717     parameter \Y_WIDTH 4'1000
5718     connect \A $9
5719     connect \B \s
5720     connect \Y $11
5721   end
5722   process $group_1
5723     assign \q 8'00000000
5724     assign \q $11
5725     sync init
5726   end
5727   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5728   wire width 8 \qn
5729   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5730   wire width 8 $13
5731   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5732   cell $not $14
5733     parameter \A_SIGNED 1'0
5734     parameter \A_WIDTH 4'1000
5735     parameter \Y_WIDTH 4'1000
5736     connect \A \q
5737     connect \Y $13
5738   end
5739   process $group_2
5740     assign \qn 8'00000000
5741     assign \qn $13
5742     sync init
5743   end
5744   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5745   wire width 8 $15
5746   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5747   cell $or $16
5748     parameter \A_SIGNED 1'0
5749     parameter \A_WIDTH 4'1000
5750     parameter \B_SIGNED 1'0
5751     parameter \B_WIDTH 4'1000
5752     parameter \Y_WIDTH 4'1000
5753     connect \A \q
5754     connect \B \q_int
5755     connect \Y $15
5756   end
5757   process $group_3
5758     assign \qlq 8'00000000
5759     assign \qlq $15
5760     sync init
5761   end
5762 end
5763 attribute \generator "nMigen"
5764 attribute \nmigen.hierarchy "top.fumemdeps.dm1"
5765 module \dm1
5766   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5767   wire width 1 input 0 \rst
5768   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5769   wire width 1 input 1 \clk
5770   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
5771   wire width 8 output 2 \st_wait_o
5772   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
5773   wire width 8 output 3 \ld_wait_o
5774   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
5775   wire width 8 input 4 \issue_i
5776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
5777   wire width 8 input 5 \go_st_i
5778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
5779   wire width 8 input 6 \go_ld_i
5780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
5781   wire width 8 input 7 \go_die_i
5782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
5783   wire width 8 input 8 \st_pend_i
5784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
5785   wire width 8 input 9 \ld_pend_i
5786   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5787   wire width 8 \st_c_s
5788   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5789   wire width 8 \st_c_r
5790   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5791   wire width 8 \st_c_qlq
5792   cell \st_c$15 \st_c
5793     connect \rst \rst
5794     connect \clk \clk
5795     connect \s \st_c_s
5796     connect \r \st_c_r
5797     connect \qlq \st_c_qlq
5798   end
5799   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5800   wire width 8 \ld_c_s
5801   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5802   wire width 8 \ld_c_r
5803   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5804   wire width 8 \ld_c_qlq
5805   cell \ld_c$16 \ld_c
5806     connect \rst \rst
5807     connect \clk \clk
5808     connect \s \ld_c_s
5809     connect \r \ld_c_r
5810     connect \qlq \ld_c_qlq
5811   end
5812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5813   wire width 8 $1
5814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5815   cell $and $2
5816     parameter \A_SIGNED 1'0
5817     parameter \A_WIDTH 4'1000
5818     parameter \B_SIGNED 1'0
5819     parameter \B_WIDTH 4'1000
5820     parameter \Y_WIDTH 4'1000
5821     connect \A \issue_i
5822     connect \B \st_pend_i
5823     connect \Y $1
5824   end
5825   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5826   wire width 9 $3
5827   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5828   wire width 8 $4
5829   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5830   cell $and $5
5831     parameter \A_SIGNED 1'0
5832     parameter \A_WIDTH 4'1000
5833     parameter \B_SIGNED 1'0
5834     parameter \B_WIDTH 4'1000
5835     parameter \Y_WIDTH 4'1000
5836     connect \A \issue_i
5837     connect \B \st_pend_i
5838     connect \Y $4
5839   end
5840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5841   wire width 9 $6
5842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5843   cell $and $7
5844     parameter \A_SIGNED 1'1
5845     parameter \A_WIDTH 4'1000
5846     parameter \B_SIGNED 1'1
5847     parameter \B_WIDTH 4'1000
5848     parameter \Y_WIDTH 4'1001
5849     connect \A $4
5850     connect \B 8'11111101
5851     connect \Y $6
5852   end
5853   connect $3 $6
5854   process $group_0
5855     assign \st_c_s 8'00000000
5856     assign \st_c_s $1
5857     assign \st_c_s $3 [7:0]
5858     sync init
5859   end
5860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5861   wire width 8 $8
5862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5863   cell $and $9
5864     parameter \A_SIGNED 1'0
5865     parameter \A_WIDTH 4'1000
5866     parameter \B_SIGNED 1'0
5867     parameter \B_WIDTH 4'1000
5868     parameter \Y_WIDTH 4'1000
5869     connect \A \issue_i
5870     connect \B \ld_pend_i
5871     connect \Y $8
5872   end
5873   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5874   wire width 9 $10
5875   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5876   wire width 8 $11
5877   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5878   cell $and $12
5879     parameter \A_SIGNED 1'0
5880     parameter \A_WIDTH 4'1000
5881     parameter \B_SIGNED 1'0
5882     parameter \B_WIDTH 4'1000
5883     parameter \Y_WIDTH 4'1000
5884     connect \A \issue_i
5885     connect \B \ld_pend_i
5886     connect \Y $11
5887   end
5888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5889   wire width 9 $13
5890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5891   cell $and $14
5892     parameter \A_SIGNED 1'1
5893     parameter \A_WIDTH 4'1000
5894     parameter \B_SIGNED 1'1
5895     parameter \B_WIDTH 4'1000
5896     parameter \Y_WIDTH 4'1001
5897     connect \A $11
5898     connect \B 8'11111101
5899     connect \Y $13
5900   end
5901   connect $10 $13
5902   process $group_1
5903     assign \ld_c_s 8'00000000
5904     assign \ld_c_s $8
5905     assign \ld_c_s $10 [7:0]
5906     sync init
5907   end
5908   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5909   wire width 8 $15
5910   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5911   cell $or $16
5912     parameter \A_SIGNED 1'0
5913     parameter \A_WIDTH 4'1000
5914     parameter \B_SIGNED 1'0
5915     parameter \B_WIDTH 4'1000
5916     parameter \Y_WIDTH 4'1000
5917     connect \A \go_ld_i
5918     connect \B \go_die_i
5919     connect \Y $15
5920   end
5921   process $group_2
5922     assign \ld_c_r 8'11111111
5923     assign \ld_c_r $15
5924     sync init
5925   end
5926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5927   wire width 8 $17
5928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5929   cell $or $18
5930     parameter \A_SIGNED 1'0
5931     parameter \A_WIDTH 4'1000
5932     parameter \B_SIGNED 1'0
5933     parameter \B_WIDTH 4'1000
5934     parameter \Y_WIDTH 4'1000
5935     connect \A \go_st_i
5936     connect \B \go_die_i
5937     connect \Y $17
5938   end
5939   process $group_3
5940     assign \st_c_r 8'11111111
5941     assign \st_c_r $17
5942     sync init
5943   end
5944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5945   wire width 8 $19
5946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5947   cell $not $20
5948     parameter \A_SIGNED 1'0
5949     parameter \A_WIDTH 4'1000
5950     parameter \Y_WIDTH 4'1000
5951     connect \A \issue_i
5952     connect \Y $19
5953   end
5954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5955   wire width 8 $21
5956   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5957   cell $and $22
5958     parameter \A_SIGNED 1'0
5959     parameter \A_WIDTH 4'1000
5960     parameter \B_SIGNED 1'0
5961     parameter \B_WIDTH 4'1000
5962     parameter \Y_WIDTH 4'1000
5963     connect \A \st_c_qlq
5964     connect \B $19
5965     connect \Y $21
5966   end
5967   process $group_4
5968     assign \st_wait_o 8'00000000
5969     assign \st_wait_o $21
5970     sync init
5971   end
5972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5973   wire width 8 $23
5974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5975   cell $not $24
5976     parameter \A_SIGNED 1'0
5977     parameter \A_WIDTH 4'1000
5978     parameter \Y_WIDTH 4'1000
5979     connect \A \issue_i
5980     connect \Y $23
5981   end
5982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5983   wire width 8 $25
5984   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5985   cell $and $26
5986     parameter \A_SIGNED 1'0
5987     parameter \A_WIDTH 4'1000
5988     parameter \B_SIGNED 1'0
5989     parameter \B_WIDTH 4'1000
5990     parameter \Y_WIDTH 4'1000
5991     connect \A \ld_c_qlq
5992     connect \B $23
5993     connect \Y $25
5994   end
5995   process $group_5
5996     assign \ld_wait_o 8'00000000
5997     assign \ld_wait_o $25
5998     sync init
5999   end
6000 end
6001 attribute \generator "nMigen"
6002 attribute \nmigen.hierarchy "top.fumemdeps.dm2.st_c"
6003 module \st_c$17
6004   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6005   wire width 1 input 0 \rst
6006   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6007   wire width 1 input 1 \clk
6008   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6009   wire width 8 input 2 \s
6010   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6011   wire width 8 input 3 \r
6012   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6013   wire width 8 output 4 \qlq
6014   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6015   wire width 8 \q_int
6016   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6017   wire width 8 \q_int$next
6018   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6019   wire width 8 $1
6020   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6021   cell $not $2
6022     parameter \A_SIGNED 1'0
6023     parameter \A_WIDTH 4'1000
6024     parameter \Y_WIDTH 4'1000
6025     connect \A \r
6026     connect \Y $1
6027   end
6028   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6029   wire width 8 $3
6030   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6031   cell $and $4
6032     parameter \A_SIGNED 1'0
6033     parameter \A_WIDTH 4'1000
6034     parameter \B_SIGNED 1'0
6035     parameter \B_WIDTH 4'1000
6036     parameter \Y_WIDTH 4'1000
6037     connect \A \q_int
6038     connect \B $1
6039     connect \Y $3
6040   end
6041   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6042   wire width 8 $5
6043   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6044   cell $or $6
6045     parameter \A_SIGNED 1'0
6046     parameter \A_WIDTH 4'1000
6047     parameter \B_SIGNED 1'0
6048     parameter \B_WIDTH 4'1000
6049     parameter \Y_WIDTH 4'1000
6050     connect \A $3
6051     connect \B \s
6052     connect \Y $5
6053   end
6054   process $group_0
6055     assign \q_int$next \q_int
6056     assign \q_int$next $5
6057     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6058     switch \rst
6059       case 1'1
6060         assign \q_int$next 8'00000000
6061     end
6062     sync init
6063       update \q_int 8'00000000
6064     sync posedge \clk
6065       update \q_int \q_int$next
6066   end
6067   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6068   wire width 8 \q
6069   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6070   wire width 8 $7
6071   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6072   cell $not $8
6073     parameter \A_SIGNED 1'0
6074     parameter \A_WIDTH 4'1000
6075     parameter \Y_WIDTH 4'1000
6076     connect \A \r
6077     connect \Y $7
6078   end
6079   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6080   wire width 8 $9
6081   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6082   cell $and $10
6083     parameter \A_SIGNED 1'0
6084     parameter \A_WIDTH 4'1000
6085     parameter \B_SIGNED 1'0
6086     parameter \B_WIDTH 4'1000
6087     parameter \Y_WIDTH 4'1000
6088     connect \A \q_int
6089     connect \B $7
6090     connect \Y $9
6091   end
6092   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6093   wire width 8 $11
6094   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6095   cell $or $12
6096     parameter \A_SIGNED 1'0
6097     parameter \A_WIDTH 4'1000
6098     parameter \B_SIGNED 1'0
6099     parameter \B_WIDTH 4'1000
6100     parameter \Y_WIDTH 4'1000
6101     connect \A $9
6102     connect \B \s
6103     connect \Y $11
6104   end
6105   process $group_1
6106     assign \q 8'00000000
6107     assign \q $11
6108     sync init
6109   end
6110   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6111   wire width 8 \qn
6112   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6113   wire width 8 $13
6114   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6115   cell $not $14
6116     parameter \A_SIGNED 1'0
6117     parameter \A_WIDTH 4'1000
6118     parameter \Y_WIDTH 4'1000
6119     connect \A \q
6120     connect \Y $13
6121   end
6122   process $group_2
6123     assign \qn 8'00000000
6124     assign \qn $13
6125     sync init
6126   end
6127   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6128   wire width 8 $15
6129   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6130   cell $or $16
6131     parameter \A_SIGNED 1'0
6132     parameter \A_WIDTH 4'1000
6133     parameter \B_SIGNED 1'0
6134     parameter \B_WIDTH 4'1000
6135     parameter \Y_WIDTH 4'1000
6136     connect \A \q
6137     connect \B \q_int
6138     connect \Y $15
6139   end
6140   process $group_3
6141     assign \qlq 8'00000000
6142     assign \qlq $15
6143     sync init
6144   end
6145 end
6146 attribute \generator "nMigen"
6147 attribute \nmigen.hierarchy "top.fumemdeps.dm2.ld_c"
6148 module \ld_c$18
6149   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6150   wire width 1 input 0 \rst
6151   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6152   wire width 1 input 1 \clk
6153   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6154   wire width 8 input 2 \s
6155   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6156   wire width 8 input 3 \r
6157   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6158   wire width 8 output 4 \qlq
6159   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6160   wire width 8 \q_int
6161   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6162   wire width 8 \q_int$next
6163   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6164   wire width 8 $1
6165   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6166   cell $not $2
6167     parameter \A_SIGNED 1'0
6168     parameter \A_WIDTH 4'1000
6169     parameter \Y_WIDTH 4'1000
6170     connect \A \r
6171     connect \Y $1
6172   end
6173   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6174   wire width 8 $3
6175   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6176   cell $and $4
6177     parameter \A_SIGNED 1'0
6178     parameter \A_WIDTH 4'1000
6179     parameter \B_SIGNED 1'0
6180     parameter \B_WIDTH 4'1000
6181     parameter \Y_WIDTH 4'1000
6182     connect \A \q_int
6183     connect \B $1
6184     connect \Y $3
6185   end
6186   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6187   wire width 8 $5
6188   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6189   cell $or $6
6190     parameter \A_SIGNED 1'0
6191     parameter \A_WIDTH 4'1000
6192     parameter \B_SIGNED 1'0
6193     parameter \B_WIDTH 4'1000
6194     parameter \Y_WIDTH 4'1000
6195     connect \A $3
6196     connect \B \s
6197     connect \Y $5
6198   end
6199   process $group_0
6200     assign \q_int$next \q_int
6201     assign \q_int$next $5
6202     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6203     switch \rst
6204       case 1'1
6205         assign \q_int$next 8'00000000
6206     end
6207     sync init
6208       update \q_int 8'00000000
6209     sync posedge \clk
6210       update \q_int \q_int$next
6211   end
6212   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6213   wire width 8 \q
6214   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6215   wire width 8 $7
6216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6217   cell $not $8
6218     parameter \A_SIGNED 1'0
6219     parameter \A_WIDTH 4'1000
6220     parameter \Y_WIDTH 4'1000
6221     connect \A \r
6222     connect \Y $7
6223   end
6224   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6225   wire width 8 $9
6226   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6227   cell $and $10
6228     parameter \A_SIGNED 1'0
6229     parameter \A_WIDTH 4'1000
6230     parameter \B_SIGNED 1'0
6231     parameter \B_WIDTH 4'1000
6232     parameter \Y_WIDTH 4'1000
6233     connect \A \q_int
6234     connect \B $7
6235     connect \Y $9
6236   end
6237   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6238   wire width 8 $11
6239   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6240   cell $or $12
6241     parameter \A_SIGNED 1'0
6242     parameter \A_WIDTH 4'1000
6243     parameter \B_SIGNED 1'0
6244     parameter \B_WIDTH 4'1000
6245     parameter \Y_WIDTH 4'1000
6246     connect \A $9
6247     connect \B \s
6248     connect \Y $11
6249   end
6250   process $group_1
6251     assign \q 8'00000000
6252     assign \q $11
6253     sync init
6254   end
6255   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6256   wire width 8 \qn
6257   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6258   wire width 8 $13
6259   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6260   cell $not $14
6261     parameter \A_SIGNED 1'0
6262     parameter \A_WIDTH 4'1000
6263     parameter \Y_WIDTH 4'1000
6264     connect \A \q
6265     connect \Y $13
6266   end
6267   process $group_2
6268     assign \qn 8'00000000
6269     assign \qn $13
6270     sync init
6271   end
6272   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6273   wire width 8 $15
6274   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6275   cell $or $16
6276     parameter \A_SIGNED 1'0
6277     parameter \A_WIDTH 4'1000
6278     parameter \B_SIGNED 1'0
6279     parameter \B_WIDTH 4'1000
6280     parameter \Y_WIDTH 4'1000
6281     connect \A \q
6282     connect \B \q_int
6283     connect \Y $15
6284   end
6285   process $group_3
6286     assign \qlq 8'00000000
6287     assign \qlq $15
6288     sync init
6289   end
6290 end
6291 attribute \generator "nMigen"
6292 attribute \nmigen.hierarchy "top.fumemdeps.dm2"
6293 module \dm2
6294   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6295   wire width 1 input 0 \rst
6296   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6297   wire width 1 input 1 \clk
6298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
6299   wire width 8 output 2 \st_wait_o
6300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
6301   wire width 8 output 3 \ld_wait_o
6302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
6303   wire width 8 input 4 \issue_i
6304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
6305   wire width 8 input 5 \go_st_i
6306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
6307   wire width 8 input 6 \go_ld_i
6308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
6309   wire width 8 input 7 \go_die_i
6310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
6311   wire width 8 input 8 \st_pend_i
6312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
6313   wire width 8 input 9 \ld_pend_i
6314   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6315   wire width 8 \st_c_s
6316   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6317   wire width 8 \st_c_r
6318   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6319   wire width 8 \st_c_qlq
6320   cell \st_c$17 \st_c
6321     connect \rst \rst
6322     connect \clk \clk
6323     connect \s \st_c_s
6324     connect \r \st_c_r
6325     connect \qlq \st_c_qlq
6326   end
6327   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6328   wire width 8 \ld_c_s
6329   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6330   wire width 8 \ld_c_r
6331   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6332   wire width 8 \ld_c_qlq
6333   cell \ld_c$18 \ld_c
6334     connect \rst \rst
6335     connect \clk \clk
6336     connect \s \ld_c_s
6337     connect \r \ld_c_r
6338     connect \qlq \ld_c_qlq
6339   end
6340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6341   wire width 8 $1
6342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6343   cell $and $2
6344     parameter \A_SIGNED 1'0
6345     parameter \A_WIDTH 4'1000
6346     parameter \B_SIGNED 1'0
6347     parameter \B_WIDTH 4'1000
6348     parameter \Y_WIDTH 4'1000
6349     connect \A \issue_i
6350     connect \B \st_pend_i
6351     connect \Y $1
6352   end
6353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6354   wire width 9 $3
6355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6356   wire width 8 $4
6357   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6358   cell $and $5
6359     parameter \A_SIGNED 1'0
6360     parameter \A_WIDTH 4'1000
6361     parameter \B_SIGNED 1'0
6362     parameter \B_WIDTH 4'1000
6363     parameter \Y_WIDTH 4'1000
6364     connect \A \issue_i
6365     connect \B \st_pend_i
6366     connect \Y $4
6367   end
6368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6369   wire width 9 $6
6370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6371   cell $and $7
6372     parameter \A_SIGNED 1'1
6373     parameter \A_WIDTH 4'1000
6374     parameter \B_SIGNED 1'1
6375     parameter \B_WIDTH 4'1000
6376     parameter \Y_WIDTH 4'1001
6377     connect \A $4
6378     connect \B 8'11111011
6379     connect \Y $6
6380   end
6381   connect $3 $6
6382   process $group_0
6383     assign \st_c_s 8'00000000
6384     assign \st_c_s $1
6385     assign \st_c_s $3 [7:0]
6386     sync init
6387   end
6388   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6389   wire width 8 $8
6390   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6391   cell $and $9
6392     parameter \A_SIGNED 1'0
6393     parameter \A_WIDTH 4'1000
6394     parameter \B_SIGNED 1'0
6395     parameter \B_WIDTH 4'1000
6396     parameter \Y_WIDTH 4'1000
6397     connect \A \issue_i
6398     connect \B \ld_pend_i
6399     connect \Y $8
6400   end
6401   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6402   wire width 9 $10
6403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6404   wire width 8 $11
6405   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6406   cell $and $12
6407     parameter \A_SIGNED 1'0
6408     parameter \A_WIDTH 4'1000
6409     parameter \B_SIGNED 1'0
6410     parameter \B_WIDTH 4'1000
6411     parameter \Y_WIDTH 4'1000
6412     connect \A \issue_i
6413     connect \B \ld_pend_i
6414     connect \Y $11
6415   end
6416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6417   wire width 9 $13
6418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6419   cell $and $14
6420     parameter \A_SIGNED 1'1
6421     parameter \A_WIDTH 4'1000
6422     parameter \B_SIGNED 1'1
6423     parameter \B_WIDTH 4'1000
6424     parameter \Y_WIDTH 4'1001
6425     connect \A $11
6426     connect \B 8'11111011
6427     connect \Y $13
6428   end
6429   connect $10 $13
6430   process $group_1
6431     assign \ld_c_s 8'00000000
6432     assign \ld_c_s $8
6433     assign \ld_c_s $10 [7:0]
6434     sync init
6435   end
6436   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6437   wire width 8 $15
6438   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6439   cell $or $16
6440     parameter \A_SIGNED 1'0
6441     parameter \A_WIDTH 4'1000
6442     parameter \B_SIGNED 1'0
6443     parameter \B_WIDTH 4'1000
6444     parameter \Y_WIDTH 4'1000
6445     connect \A \go_ld_i
6446     connect \B \go_die_i
6447     connect \Y $15
6448   end
6449   process $group_2
6450     assign \ld_c_r 8'11111111
6451     assign \ld_c_r $15
6452     sync init
6453   end
6454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6455   wire width 8 $17
6456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6457   cell $or $18
6458     parameter \A_SIGNED 1'0
6459     parameter \A_WIDTH 4'1000
6460     parameter \B_SIGNED 1'0
6461     parameter \B_WIDTH 4'1000
6462     parameter \Y_WIDTH 4'1000
6463     connect \A \go_st_i
6464     connect \B \go_die_i
6465     connect \Y $17
6466   end
6467   process $group_3
6468     assign \st_c_r 8'11111111
6469     assign \st_c_r $17
6470     sync init
6471   end
6472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6473   wire width 8 $19
6474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6475   cell $not $20
6476     parameter \A_SIGNED 1'0
6477     parameter \A_WIDTH 4'1000
6478     parameter \Y_WIDTH 4'1000
6479     connect \A \issue_i
6480     connect \Y $19
6481   end
6482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6483   wire width 8 $21
6484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6485   cell $and $22
6486     parameter \A_SIGNED 1'0
6487     parameter \A_WIDTH 4'1000
6488     parameter \B_SIGNED 1'0
6489     parameter \B_WIDTH 4'1000
6490     parameter \Y_WIDTH 4'1000
6491     connect \A \st_c_qlq
6492     connect \B $19
6493     connect \Y $21
6494   end
6495   process $group_4
6496     assign \st_wait_o 8'00000000
6497     assign \st_wait_o $21
6498     sync init
6499   end
6500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6501   wire width 8 $23
6502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6503   cell $not $24
6504     parameter \A_SIGNED 1'0
6505     parameter \A_WIDTH 4'1000
6506     parameter \Y_WIDTH 4'1000
6507     connect \A \issue_i
6508     connect \Y $23
6509   end
6510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6511   wire width 8 $25
6512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6513   cell $and $26
6514     parameter \A_SIGNED 1'0
6515     parameter \A_WIDTH 4'1000
6516     parameter \B_SIGNED 1'0
6517     parameter \B_WIDTH 4'1000
6518     parameter \Y_WIDTH 4'1000
6519     connect \A \ld_c_qlq
6520     connect \B $23
6521     connect \Y $25
6522   end
6523   process $group_5
6524     assign \ld_wait_o 8'00000000
6525     assign \ld_wait_o $25
6526     sync init
6527   end
6528 end
6529 attribute \generator "nMigen"
6530 attribute \nmigen.hierarchy "top.fumemdeps.dm3.st_c"
6531 module \st_c$19
6532   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6533   wire width 1 input 0 \rst
6534   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6535   wire width 1 input 1 \clk
6536   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6537   wire width 8 input 2 \s
6538   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6539   wire width 8 input 3 \r
6540   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6541   wire width 8 output 4 \qlq
6542   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6543   wire width 8 \q_int
6544   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6545   wire width 8 \q_int$next
6546   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6547   wire width 8 $1
6548   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6549   cell $not $2
6550     parameter \A_SIGNED 1'0
6551     parameter \A_WIDTH 4'1000
6552     parameter \Y_WIDTH 4'1000
6553     connect \A \r
6554     connect \Y $1
6555   end
6556   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6557   wire width 8 $3
6558   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6559   cell $and $4
6560     parameter \A_SIGNED 1'0
6561     parameter \A_WIDTH 4'1000
6562     parameter \B_SIGNED 1'0
6563     parameter \B_WIDTH 4'1000
6564     parameter \Y_WIDTH 4'1000
6565     connect \A \q_int
6566     connect \B $1
6567     connect \Y $3
6568   end
6569   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6570   wire width 8 $5
6571   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6572   cell $or $6
6573     parameter \A_SIGNED 1'0
6574     parameter \A_WIDTH 4'1000
6575     parameter \B_SIGNED 1'0
6576     parameter \B_WIDTH 4'1000
6577     parameter \Y_WIDTH 4'1000
6578     connect \A $3
6579     connect \B \s
6580     connect \Y $5
6581   end
6582   process $group_0
6583     assign \q_int$next \q_int
6584     assign \q_int$next $5
6585     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6586     switch \rst
6587       case 1'1
6588         assign \q_int$next 8'00000000
6589     end
6590     sync init
6591       update \q_int 8'00000000
6592     sync posedge \clk
6593       update \q_int \q_int$next
6594   end
6595   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6596   wire width 8 \q
6597   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6598   wire width 8 $7
6599   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6600   cell $not $8
6601     parameter \A_SIGNED 1'0
6602     parameter \A_WIDTH 4'1000
6603     parameter \Y_WIDTH 4'1000
6604     connect \A \r
6605     connect \Y $7
6606   end
6607   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6608   wire width 8 $9
6609   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6610   cell $and $10
6611     parameter \A_SIGNED 1'0
6612     parameter \A_WIDTH 4'1000
6613     parameter \B_SIGNED 1'0
6614     parameter \B_WIDTH 4'1000
6615     parameter \Y_WIDTH 4'1000
6616     connect \A \q_int
6617     connect \B $7
6618     connect \Y $9
6619   end
6620   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6621   wire width 8 $11
6622   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6623   cell $or $12
6624     parameter \A_SIGNED 1'0
6625     parameter \A_WIDTH 4'1000
6626     parameter \B_SIGNED 1'0
6627     parameter \B_WIDTH 4'1000
6628     parameter \Y_WIDTH 4'1000
6629     connect \A $9
6630     connect \B \s
6631     connect \Y $11
6632   end
6633   process $group_1
6634     assign \q 8'00000000
6635     assign \q $11
6636     sync init
6637   end
6638   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6639   wire width 8 \qn
6640   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6641   wire width 8 $13
6642   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6643   cell $not $14
6644     parameter \A_SIGNED 1'0
6645     parameter \A_WIDTH 4'1000
6646     parameter \Y_WIDTH 4'1000
6647     connect \A \q
6648     connect \Y $13
6649   end
6650   process $group_2
6651     assign \qn 8'00000000
6652     assign \qn $13
6653     sync init
6654   end
6655   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6656   wire width 8 $15
6657   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6658   cell $or $16
6659     parameter \A_SIGNED 1'0
6660     parameter \A_WIDTH 4'1000
6661     parameter \B_SIGNED 1'0
6662     parameter \B_WIDTH 4'1000
6663     parameter \Y_WIDTH 4'1000
6664     connect \A \q
6665     connect \B \q_int
6666     connect \Y $15
6667   end
6668   process $group_3
6669     assign \qlq 8'00000000
6670     assign \qlq $15
6671     sync init
6672   end
6673 end
6674 attribute \generator "nMigen"
6675 attribute \nmigen.hierarchy "top.fumemdeps.dm3.ld_c"
6676 module \ld_c$20
6677   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6678   wire width 1 input 0 \rst
6679   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6680   wire width 1 input 1 \clk
6681   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6682   wire width 8 input 2 \s
6683   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6684   wire width 8 input 3 \r
6685   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6686   wire width 8 output 4 \qlq
6687   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6688   wire width 8 \q_int
6689   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6690   wire width 8 \q_int$next
6691   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6692   wire width 8 $1
6693   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6694   cell $not $2
6695     parameter \A_SIGNED 1'0
6696     parameter \A_WIDTH 4'1000
6697     parameter \Y_WIDTH 4'1000
6698     connect \A \r
6699     connect \Y $1
6700   end
6701   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6702   wire width 8 $3
6703   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6704   cell $and $4
6705     parameter \A_SIGNED 1'0
6706     parameter \A_WIDTH 4'1000
6707     parameter \B_SIGNED 1'0
6708     parameter \B_WIDTH 4'1000
6709     parameter \Y_WIDTH 4'1000
6710     connect \A \q_int
6711     connect \B $1
6712     connect \Y $3
6713   end
6714   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6715   wire width 8 $5
6716   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6717   cell $or $6
6718     parameter \A_SIGNED 1'0
6719     parameter \A_WIDTH 4'1000
6720     parameter \B_SIGNED 1'0
6721     parameter \B_WIDTH 4'1000
6722     parameter \Y_WIDTH 4'1000
6723     connect \A $3
6724     connect \B \s
6725     connect \Y $5
6726   end
6727   process $group_0
6728     assign \q_int$next \q_int
6729     assign \q_int$next $5
6730     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6731     switch \rst
6732       case 1'1
6733         assign \q_int$next 8'00000000
6734     end
6735     sync init
6736       update \q_int 8'00000000
6737     sync posedge \clk
6738       update \q_int \q_int$next
6739   end
6740   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6741   wire width 8 \q
6742   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6743   wire width 8 $7
6744   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6745   cell $not $8
6746     parameter \A_SIGNED 1'0
6747     parameter \A_WIDTH 4'1000
6748     parameter \Y_WIDTH 4'1000
6749     connect \A \r
6750     connect \Y $7
6751   end
6752   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6753   wire width 8 $9
6754   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6755   cell $and $10
6756     parameter \A_SIGNED 1'0
6757     parameter \A_WIDTH 4'1000
6758     parameter \B_SIGNED 1'0
6759     parameter \B_WIDTH 4'1000
6760     parameter \Y_WIDTH 4'1000
6761     connect \A \q_int
6762     connect \B $7
6763     connect \Y $9
6764   end
6765   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6766   wire width 8 $11
6767   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6768   cell $or $12
6769     parameter \A_SIGNED 1'0
6770     parameter \A_WIDTH 4'1000
6771     parameter \B_SIGNED 1'0
6772     parameter \B_WIDTH 4'1000
6773     parameter \Y_WIDTH 4'1000
6774     connect \A $9
6775     connect \B \s
6776     connect \Y $11
6777   end
6778   process $group_1
6779     assign \q 8'00000000
6780     assign \q $11
6781     sync init
6782   end
6783   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6784   wire width 8 \qn
6785   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6786   wire width 8 $13
6787   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6788   cell $not $14
6789     parameter \A_SIGNED 1'0
6790     parameter \A_WIDTH 4'1000
6791     parameter \Y_WIDTH 4'1000
6792     connect \A \q
6793     connect \Y $13
6794   end
6795   process $group_2
6796     assign \qn 8'00000000
6797     assign \qn $13
6798     sync init
6799   end
6800   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6801   wire width 8 $15
6802   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6803   cell $or $16
6804     parameter \A_SIGNED 1'0
6805     parameter \A_WIDTH 4'1000
6806     parameter \B_SIGNED 1'0
6807     parameter \B_WIDTH 4'1000
6808     parameter \Y_WIDTH 4'1000
6809     connect \A \q
6810     connect \B \q_int
6811     connect \Y $15
6812   end
6813   process $group_3
6814     assign \qlq 8'00000000
6815     assign \qlq $15
6816     sync init
6817   end
6818 end
6819 attribute \generator "nMigen"
6820 attribute \nmigen.hierarchy "top.fumemdeps.dm3"
6821 module \dm3
6822   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6823   wire width 1 input 0 \rst
6824   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6825   wire width 1 input 1 \clk
6826   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
6827   wire width 8 output 2 \st_wait_o
6828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
6829   wire width 8 output 3 \ld_wait_o
6830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
6831   wire width 8 input 4 \issue_i
6832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
6833   wire width 8 input 5 \go_st_i
6834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
6835   wire width 8 input 6 \go_ld_i
6836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
6837   wire width 8 input 7 \go_die_i
6838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
6839   wire width 8 input 8 \st_pend_i
6840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
6841   wire width 8 input 9 \ld_pend_i
6842   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6843   wire width 8 \st_c_s
6844   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6845   wire width 8 \st_c_r
6846   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6847   wire width 8 \st_c_qlq
6848   cell \st_c$19 \st_c
6849     connect \rst \rst
6850     connect \clk \clk
6851     connect \s \st_c_s
6852     connect \r \st_c_r
6853     connect \qlq \st_c_qlq
6854   end
6855   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6856   wire width 8 \ld_c_s
6857   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6858   wire width 8 \ld_c_r
6859   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6860   wire width 8 \ld_c_qlq
6861   cell \ld_c$20 \ld_c
6862     connect \rst \rst
6863     connect \clk \clk
6864     connect \s \ld_c_s
6865     connect \r \ld_c_r
6866     connect \qlq \ld_c_qlq
6867   end
6868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6869   wire width 8 $1
6870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6871   cell $and $2
6872     parameter \A_SIGNED 1'0
6873     parameter \A_WIDTH 4'1000
6874     parameter \B_SIGNED 1'0
6875     parameter \B_WIDTH 4'1000
6876     parameter \Y_WIDTH 4'1000
6877     connect \A \issue_i
6878     connect \B \st_pend_i
6879     connect \Y $1
6880   end
6881   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6882   wire width 9 $3
6883   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6884   wire width 8 $4
6885   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6886   cell $and $5
6887     parameter \A_SIGNED 1'0
6888     parameter \A_WIDTH 4'1000
6889     parameter \B_SIGNED 1'0
6890     parameter \B_WIDTH 4'1000
6891     parameter \Y_WIDTH 4'1000
6892     connect \A \issue_i
6893     connect \B \st_pend_i
6894     connect \Y $4
6895   end
6896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6897   wire width 9 $6
6898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6899   cell $and $7
6900     parameter \A_SIGNED 1'1
6901     parameter \A_WIDTH 4'1000
6902     parameter \B_SIGNED 1'1
6903     parameter \B_WIDTH 4'1000
6904     parameter \Y_WIDTH 4'1001
6905     connect \A $4
6906     connect \B 8'11110111
6907     connect \Y $6
6908   end
6909   connect $3 $6
6910   process $group_0
6911     assign \st_c_s 8'00000000
6912     assign \st_c_s $1
6913     assign \st_c_s $3 [7:0]
6914     sync init
6915   end
6916   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6917   wire width 8 $8
6918   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6919   cell $and $9
6920     parameter \A_SIGNED 1'0
6921     parameter \A_WIDTH 4'1000
6922     parameter \B_SIGNED 1'0
6923     parameter \B_WIDTH 4'1000
6924     parameter \Y_WIDTH 4'1000
6925     connect \A \issue_i
6926     connect \B \ld_pend_i
6927     connect \Y $8
6928   end
6929   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6930   wire width 9 $10
6931   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6932   wire width 8 $11
6933   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6934   cell $and $12
6935     parameter \A_SIGNED 1'0
6936     parameter \A_WIDTH 4'1000
6937     parameter \B_SIGNED 1'0
6938     parameter \B_WIDTH 4'1000
6939     parameter \Y_WIDTH 4'1000
6940     connect \A \issue_i
6941     connect \B \ld_pend_i
6942     connect \Y $11
6943   end
6944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6945   wire width 9 $13
6946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6947   cell $and $14
6948     parameter \A_SIGNED 1'1
6949     parameter \A_WIDTH 4'1000
6950     parameter \B_SIGNED 1'1
6951     parameter \B_WIDTH 4'1000
6952     parameter \Y_WIDTH 4'1001
6953     connect \A $11
6954     connect \B 8'11110111
6955     connect \Y $13
6956   end
6957   connect $10 $13
6958   process $group_1
6959     assign \ld_c_s 8'00000000
6960     assign \ld_c_s $8
6961     assign \ld_c_s $10 [7:0]
6962     sync init
6963   end
6964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6965   wire width 8 $15
6966   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6967   cell $or $16
6968     parameter \A_SIGNED 1'0
6969     parameter \A_WIDTH 4'1000
6970     parameter \B_SIGNED 1'0
6971     parameter \B_WIDTH 4'1000
6972     parameter \Y_WIDTH 4'1000
6973     connect \A \go_ld_i
6974     connect \B \go_die_i
6975     connect \Y $15
6976   end
6977   process $group_2
6978     assign \ld_c_r 8'11111111
6979     assign \ld_c_r $15
6980     sync init
6981   end
6982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6983   wire width 8 $17
6984   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6985   cell $or $18
6986     parameter \A_SIGNED 1'0
6987     parameter \A_WIDTH 4'1000
6988     parameter \B_SIGNED 1'0
6989     parameter \B_WIDTH 4'1000
6990     parameter \Y_WIDTH 4'1000
6991     connect \A \go_st_i
6992     connect \B \go_die_i
6993     connect \Y $17
6994   end
6995   process $group_3
6996     assign \st_c_r 8'11111111
6997     assign \st_c_r $17
6998     sync init
6999   end
7000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7001   wire width 8 $19
7002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7003   cell $not $20
7004     parameter \A_SIGNED 1'0
7005     parameter \A_WIDTH 4'1000
7006     parameter \Y_WIDTH 4'1000
7007     connect \A \issue_i
7008     connect \Y $19
7009   end
7010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7011   wire width 8 $21
7012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7013   cell $and $22
7014     parameter \A_SIGNED 1'0
7015     parameter \A_WIDTH 4'1000
7016     parameter \B_SIGNED 1'0
7017     parameter \B_WIDTH 4'1000
7018     parameter \Y_WIDTH 4'1000
7019     connect \A \st_c_qlq
7020     connect \B $19
7021     connect \Y $21
7022   end
7023   process $group_4
7024     assign \st_wait_o 8'00000000
7025     assign \st_wait_o $21
7026     sync init
7027   end
7028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7029   wire width 8 $23
7030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7031   cell $not $24
7032     parameter \A_SIGNED 1'0
7033     parameter \A_WIDTH 4'1000
7034     parameter \Y_WIDTH 4'1000
7035     connect \A \issue_i
7036     connect \Y $23
7037   end
7038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7039   wire width 8 $25
7040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7041   cell $and $26
7042     parameter \A_SIGNED 1'0
7043     parameter \A_WIDTH 4'1000
7044     parameter \B_SIGNED 1'0
7045     parameter \B_WIDTH 4'1000
7046     parameter \Y_WIDTH 4'1000
7047     connect \A \ld_c_qlq
7048     connect \B $23
7049     connect \Y $25
7050   end
7051   process $group_5
7052     assign \ld_wait_o 8'00000000
7053     assign \ld_wait_o $25
7054     sync init
7055   end
7056 end
7057 attribute \generator "nMigen"
7058 attribute \nmigen.hierarchy "top.fumemdeps.dm4.st_c"
7059 module \st_c$21
7060   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7061   wire width 1 input 0 \rst
7062   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7063   wire width 1 input 1 \clk
7064   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7065   wire width 8 input 2 \s
7066   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7067   wire width 8 input 3 \r
7068   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7069   wire width 8 output 4 \qlq
7070   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7071   wire width 8 \q_int
7072   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7073   wire width 8 \q_int$next
7074   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7075   wire width 8 $1
7076   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7077   cell $not $2
7078     parameter \A_SIGNED 1'0
7079     parameter \A_WIDTH 4'1000
7080     parameter \Y_WIDTH 4'1000
7081     connect \A \r
7082     connect \Y $1
7083   end
7084   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7085   wire width 8 $3
7086   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7087   cell $and $4
7088     parameter \A_SIGNED 1'0
7089     parameter \A_WIDTH 4'1000
7090     parameter \B_SIGNED 1'0
7091     parameter \B_WIDTH 4'1000
7092     parameter \Y_WIDTH 4'1000
7093     connect \A \q_int
7094     connect \B $1
7095     connect \Y $3
7096   end
7097   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7098   wire width 8 $5
7099   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7100   cell $or $6
7101     parameter \A_SIGNED 1'0
7102     parameter \A_WIDTH 4'1000
7103     parameter \B_SIGNED 1'0
7104     parameter \B_WIDTH 4'1000
7105     parameter \Y_WIDTH 4'1000
7106     connect \A $3
7107     connect \B \s
7108     connect \Y $5
7109   end
7110   process $group_0
7111     assign \q_int$next \q_int
7112     assign \q_int$next $5
7113     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7114     switch \rst
7115       case 1'1
7116         assign \q_int$next 8'00000000
7117     end
7118     sync init
7119       update \q_int 8'00000000
7120     sync posedge \clk
7121       update \q_int \q_int$next
7122   end
7123   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7124   wire width 8 \q
7125   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7126   wire width 8 $7
7127   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7128   cell $not $8
7129     parameter \A_SIGNED 1'0
7130     parameter \A_WIDTH 4'1000
7131     parameter \Y_WIDTH 4'1000
7132     connect \A \r
7133     connect \Y $7
7134   end
7135   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7136   wire width 8 $9
7137   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7138   cell $and $10
7139     parameter \A_SIGNED 1'0
7140     parameter \A_WIDTH 4'1000
7141     parameter \B_SIGNED 1'0
7142     parameter \B_WIDTH 4'1000
7143     parameter \Y_WIDTH 4'1000
7144     connect \A \q_int
7145     connect \B $7
7146     connect \Y $9
7147   end
7148   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7149   wire width 8 $11
7150   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7151   cell $or $12
7152     parameter \A_SIGNED 1'0
7153     parameter \A_WIDTH 4'1000
7154     parameter \B_SIGNED 1'0
7155     parameter \B_WIDTH 4'1000
7156     parameter \Y_WIDTH 4'1000
7157     connect \A $9
7158     connect \B \s
7159     connect \Y $11
7160   end
7161   process $group_1
7162     assign \q 8'00000000
7163     assign \q $11
7164     sync init
7165   end
7166   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7167   wire width 8 \qn
7168   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7169   wire width 8 $13
7170   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7171   cell $not $14
7172     parameter \A_SIGNED 1'0
7173     parameter \A_WIDTH 4'1000
7174     parameter \Y_WIDTH 4'1000
7175     connect \A \q
7176     connect \Y $13
7177   end
7178   process $group_2
7179     assign \qn 8'00000000
7180     assign \qn $13
7181     sync init
7182   end
7183   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7184   wire width 8 $15
7185   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7186   cell $or $16
7187     parameter \A_SIGNED 1'0
7188     parameter \A_WIDTH 4'1000
7189     parameter \B_SIGNED 1'0
7190     parameter \B_WIDTH 4'1000
7191     parameter \Y_WIDTH 4'1000
7192     connect \A \q
7193     connect \B \q_int
7194     connect \Y $15
7195   end
7196   process $group_3
7197     assign \qlq 8'00000000
7198     assign \qlq $15
7199     sync init
7200   end
7201 end
7202 attribute \generator "nMigen"
7203 attribute \nmigen.hierarchy "top.fumemdeps.dm4.ld_c"
7204 module \ld_c$22
7205   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7206   wire width 1 input 0 \rst
7207   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7208   wire width 1 input 1 \clk
7209   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7210   wire width 8 input 2 \s
7211   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7212   wire width 8 input 3 \r
7213   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7214   wire width 8 output 4 \qlq
7215   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7216   wire width 8 \q_int
7217   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7218   wire width 8 \q_int$next
7219   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7220   wire width 8 $1
7221   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7222   cell $not $2
7223     parameter \A_SIGNED 1'0
7224     parameter \A_WIDTH 4'1000
7225     parameter \Y_WIDTH 4'1000
7226     connect \A \r
7227     connect \Y $1
7228   end
7229   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7230   wire width 8 $3
7231   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7232   cell $and $4
7233     parameter \A_SIGNED 1'0
7234     parameter \A_WIDTH 4'1000
7235     parameter \B_SIGNED 1'0
7236     parameter \B_WIDTH 4'1000
7237     parameter \Y_WIDTH 4'1000
7238     connect \A \q_int
7239     connect \B $1
7240     connect \Y $3
7241   end
7242   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7243   wire width 8 $5
7244   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7245   cell $or $6
7246     parameter \A_SIGNED 1'0
7247     parameter \A_WIDTH 4'1000
7248     parameter \B_SIGNED 1'0
7249     parameter \B_WIDTH 4'1000
7250     parameter \Y_WIDTH 4'1000
7251     connect \A $3
7252     connect \B \s
7253     connect \Y $5
7254   end
7255   process $group_0
7256     assign \q_int$next \q_int
7257     assign \q_int$next $5
7258     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7259     switch \rst
7260       case 1'1
7261         assign \q_int$next 8'00000000
7262     end
7263     sync init
7264       update \q_int 8'00000000
7265     sync posedge \clk
7266       update \q_int \q_int$next
7267   end
7268   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7269   wire width 8 \q
7270   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7271   wire width 8 $7
7272   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7273   cell $not $8
7274     parameter \A_SIGNED 1'0
7275     parameter \A_WIDTH 4'1000
7276     parameter \Y_WIDTH 4'1000
7277     connect \A \r
7278     connect \Y $7
7279   end
7280   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7281   wire width 8 $9
7282   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7283   cell $and $10
7284     parameter \A_SIGNED 1'0
7285     parameter \A_WIDTH 4'1000
7286     parameter \B_SIGNED 1'0
7287     parameter \B_WIDTH 4'1000
7288     parameter \Y_WIDTH 4'1000
7289     connect \A \q_int
7290     connect \B $7
7291     connect \Y $9
7292   end
7293   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7294   wire width 8 $11
7295   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7296   cell $or $12
7297     parameter \A_SIGNED 1'0
7298     parameter \A_WIDTH 4'1000
7299     parameter \B_SIGNED 1'0
7300     parameter \B_WIDTH 4'1000
7301     parameter \Y_WIDTH 4'1000
7302     connect \A $9
7303     connect \B \s
7304     connect \Y $11
7305   end
7306   process $group_1
7307     assign \q 8'00000000
7308     assign \q $11
7309     sync init
7310   end
7311   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7312   wire width 8 \qn
7313   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7314   wire width 8 $13
7315   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7316   cell $not $14
7317     parameter \A_SIGNED 1'0
7318     parameter \A_WIDTH 4'1000
7319     parameter \Y_WIDTH 4'1000
7320     connect \A \q
7321     connect \Y $13
7322   end
7323   process $group_2
7324     assign \qn 8'00000000
7325     assign \qn $13
7326     sync init
7327   end
7328   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7329   wire width 8 $15
7330   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7331   cell $or $16
7332     parameter \A_SIGNED 1'0
7333     parameter \A_WIDTH 4'1000
7334     parameter \B_SIGNED 1'0
7335     parameter \B_WIDTH 4'1000
7336     parameter \Y_WIDTH 4'1000
7337     connect \A \q
7338     connect \B \q_int
7339     connect \Y $15
7340   end
7341   process $group_3
7342     assign \qlq 8'00000000
7343     assign \qlq $15
7344     sync init
7345   end
7346 end
7347 attribute \generator "nMigen"
7348 attribute \nmigen.hierarchy "top.fumemdeps.dm4"
7349 module \dm4
7350   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7351   wire width 1 input 0 \rst
7352   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7353   wire width 1 input 1 \clk
7354   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
7355   wire width 8 output 2 \st_wait_o
7356   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
7357   wire width 8 output 3 \ld_wait_o
7358   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
7359   wire width 8 input 4 \issue_i
7360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
7361   wire width 8 input 5 \go_st_i
7362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
7363   wire width 8 input 6 \go_ld_i
7364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
7365   wire width 8 input 7 \go_die_i
7366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
7367   wire width 8 input 8 \st_pend_i
7368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
7369   wire width 8 input 9 \ld_pend_i
7370   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7371   wire width 8 \st_c_s
7372   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7373   wire width 8 \st_c_r
7374   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7375   wire width 8 \st_c_qlq
7376   cell \st_c$21 \st_c
7377     connect \rst \rst
7378     connect \clk \clk
7379     connect \s \st_c_s
7380     connect \r \st_c_r
7381     connect \qlq \st_c_qlq
7382   end
7383   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7384   wire width 8 \ld_c_s
7385   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7386   wire width 8 \ld_c_r
7387   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7388   wire width 8 \ld_c_qlq
7389   cell \ld_c$22 \ld_c
7390     connect \rst \rst
7391     connect \clk \clk
7392     connect \s \ld_c_s
7393     connect \r \ld_c_r
7394     connect \qlq \ld_c_qlq
7395   end
7396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7397   wire width 8 $1
7398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7399   cell $and $2
7400     parameter \A_SIGNED 1'0
7401     parameter \A_WIDTH 4'1000
7402     parameter \B_SIGNED 1'0
7403     parameter \B_WIDTH 4'1000
7404     parameter \Y_WIDTH 4'1000
7405     connect \A \issue_i
7406     connect \B \st_pend_i
7407     connect \Y $1
7408   end
7409   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7410   wire width 9 $3
7411   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7412   wire width 8 $4
7413   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7414   cell $and $5
7415     parameter \A_SIGNED 1'0
7416     parameter \A_WIDTH 4'1000
7417     parameter \B_SIGNED 1'0
7418     parameter \B_WIDTH 4'1000
7419     parameter \Y_WIDTH 4'1000
7420     connect \A \issue_i
7421     connect \B \st_pend_i
7422     connect \Y $4
7423   end
7424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7425   wire width 9 $6
7426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7427   cell $and $7
7428     parameter \A_SIGNED 1'1
7429     parameter \A_WIDTH 4'1000
7430     parameter \B_SIGNED 1'1
7431     parameter \B_WIDTH 4'1000
7432     parameter \Y_WIDTH 4'1001
7433     connect \A $4
7434     connect \B 8'11101111
7435     connect \Y $6
7436   end
7437   connect $3 $6
7438   process $group_0
7439     assign \st_c_s 8'00000000
7440     assign \st_c_s $1
7441     assign \st_c_s $3 [7:0]
7442     sync init
7443   end
7444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7445   wire width 8 $8
7446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7447   cell $and $9
7448     parameter \A_SIGNED 1'0
7449     parameter \A_WIDTH 4'1000
7450     parameter \B_SIGNED 1'0
7451     parameter \B_WIDTH 4'1000
7452     parameter \Y_WIDTH 4'1000
7453     connect \A \issue_i
7454     connect \B \ld_pend_i
7455     connect \Y $8
7456   end
7457   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7458   wire width 9 $10
7459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7460   wire width 8 $11
7461   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7462   cell $and $12
7463     parameter \A_SIGNED 1'0
7464     parameter \A_WIDTH 4'1000
7465     parameter \B_SIGNED 1'0
7466     parameter \B_WIDTH 4'1000
7467     parameter \Y_WIDTH 4'1000
7468     connect \A \issue_i
7469     connect \B \ld_pend_i
7470     connect \Y $11
7471   end
7472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7473   wire width 9 $13
7474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7475   cell $and $14
7476     parameter \A_SIGNED 1'1
7477     parameter \A_WIDTH 4'1000
7478     parameter \B_SIGNED 1'1
7479     parameter \B_WIDTH 4'1000
7480     parameter \Y_WIDTH 4'1001
7481     connect \A $11
7482     connect \B 8'11101111
7483     connect \Y $13
7484   end
7485   connect $10 $13
7486   process $group_1
7487     assign \ld_c_s 8'00000000
7488     assign \ld_c_s $8
7489     assign \ld_c_s $10 [7:0]
7490     sync init
7491   end
7492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
7493   wire width 8 $15
7494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
7495   cell $or $16
7496     parameter \A_SIGNED 1'0
7497     parameter \A_WIDTH 4'1000
7498     parameter \B_SIGNED 1'0
7499     parameter \B_WIDTH 4'1000
7500     parameter \Y_WIDTH 4'1000
7501     connect \A \go_ld_i
7502     connect \B \go_die_i
7503     connect \Y $15
7504   end
7505   process $group_2
7506     assign \ld_c_r 8'11111111
7507     assign \ld_c_r $15
7508     sync init
7509   end
7510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
7511   wire width 8 $17
7512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
7513   cell $or $18
7514     parameter \A_SIGNED 1'0
7515     parameter \A_WIDTH 4'1000
7516     parameter \B_SIGNED 1'0
7517     parameter \B_WIDTH 4'1000
7518     parameter \Y_WIDTH 4'1000
7519     connect \A \go_st_i
7520     connect \B \go_die_i
7521     connect \Y $17
7522   end
7523   process $group_3
7524     assign \st_c_r 8'11111111
7525     assign \st_c_r $17
7526     sync init
7527   end
7528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7529   wire width 8 $19
7530   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7531   cell $not $20
7532     parameter \A_SIGNED 1'0
7533     parameter \A_WIDTH 4'1000
7534     parameter \Y_WIDTH 4'1000
7535     connect \A \issue_i
7536     connect \Y $19
7537   end
7538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7539   wire width 8 $21
7540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7541   cell $and $22
7542     parameter \A_SIGNED 1'0
7543     parameter \A_WIDTH 4'1000
7544     parameter \B_SIGNED 1'0
7545     parameter \B_WIDTH 4'1000
7546     parameter \Y_WIDTH 4'1000
7547     connect \A \st_c_qlq
7548     connect \B $19
7549     connect \Y $21
7550   end
7551   process $group_4
7552     assign \st_wait_o 8'00000000
7553     assign \st_wait_o $21
7554     sync init
7555   end
7556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7557   wire width 8 $23
7558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7559   cell $not $24
7560     parameter \A_SIGNED 1'0
7561     parameter \A_WIDTH 4'1000
7562     parameter \Y_WIDTH 4'1000
7563     connect \A \issue_i
7564     connect \Y $23
7565   end
7566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7567   wire width 8 $25
7568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7569   cell $and $26
7570     parameter \A_SIGNED 1'0
7571     parameter \A_WIDTH 4'1000
7572     parameter \B_SIGNED 1'0
7573     parameter \B_WIDTH 4'1000
7574     parameter \Y_WIDTH 4'1000
7575     connect \A \ld_c_qlq
7576     connect \B $23
7577     connect \Y $25
7578   end
7579   process $group_5
7580     assign \ld_wait_o 8'00000000
7581     assign \ld_wait_o $25
7582     sync init
7583   end
7584 end
7585 attribute \generator "nMigen"
7586 attribute \nmigen.hierarchy "top.fumemdeps.dm5.st_c"
7587 module \st_c$23
7588   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7589   wire width 1 input 0 \rst
7590   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7591   wire width 1 input 1 \clk
7592   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7593   wire width 8 input 2 \s
7594   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7595   wire width 8 input 3 \r
7596   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7597   wire width 8 output 4 \qlq
7598   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7599   wire width 8 \q_int
7600   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7601   wire width 8 \q_int$next
7602   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7603   wire width 8 $1
7604   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7605   cell $not $2
7606     parameter \A_SIGNED 1'0
7607     parameter \A_WIDTH 4'1000
7608     parameter \Y_WIDTH 4'1000
7609     connect \A \r
7610     connect \Y $1
7611   end
7612   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7613   wire width 8 $3
7614   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7615   cell $and $4
7616     parameter \A_SIGNED 1'0
7617     parameter \A_WIDTH 4'1000
7618     parameter \B_SIGNED 1'0
7619     parameter \B_WIDTH 4'1000
7620     parameter \Y_WIDTH 4'1000
7621     connect \A \q_int
7622     connect \B $1
7623     connect \Y $3
7624   end
7625   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7626   wire width 8 $5
7627   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7628   cell $or $6
7629     parameter \A_SIGNED 1'0
7630     parameter \A_WIDTH 4'1000
7631     parameter \B_SIGNED 1'0
7632     parameter \B_WIDTH 4'1000
7633     parameter \Y_WIDTH 4'1000
7634     connect \A $3
7635     connect \B \s
7636     connect \Y $5
7637   end
7638   process $group_0
7639     assign \q_int$next \q_int
7640     assign \q_int$next $5
7641     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7642     switch \rst
7643       case 1'1
7644         assign \q_int$next 8'00000000
7645     end
7646     sync init
7647       update \q_int 8'00000000
7648     sync posedge \clk
7649       update \q_int \q_int$next
7650   end
7651   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7652   wire width 8 \q
7653   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7654   wire width 8 $7
7655   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7656   cell $not $8
7657     parameter \A_SIGNED 1'0
7658     parameter \A_WIDTH 4'1000
7659     parameter \Y_WIDTH 4'1000
7660     connect \A \r
7661     connect \Y $7
7662   end
7663   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7664   wire width 8 $9
7665   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7666   cell $and $10
7667     parameter \A_SIGNED 1'0
7668     parameter \A_WIDTH 4'1000
7669     parameter \B_SIGNED 1'0
7670     parameter \B_WIDTH 4'1000
7671     parameter \Y_WIDTH 4'1000
7672     connect \A \q_int
7673     connect \B $7
7674     connect \Y $9
7675   end
7676   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7677   wire width 8 $11
7678   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7679   cell $or $12
7680     parameter \A_SIGNED 1'0
7681     parameter \A_WIDTH 4'1000
7682     parameter \B_SIGNED 1'0
7683     parameter \B_WIDTH 4'1000
7684     parameter \Y_WIDTH 4'1000
7685     connect \A $9
7686     connect \B \s
7687     connect \Y $11
7688   end
7689   process $group_1
7690     assign \q 8'00000000
7691     assign \q $11
7692     sync init
7693   end
7694   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7695   wire width 8 \qn
7696   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7697   wire width 8 $13
7698   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7699   cell $not $14
7700     parameter \A_SIGNED 1'0
7701     parameter \A_WIDTH 4'1000
7702     parameter \Y_WIDTH 4'1000
7703     connect \A \q
7704     connect \Y $13
7705   end
7706   process $group_2
7707     assign \qn 8'00000000
7708     assign \qn $13
7709     sync init
7710   end
7711   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7712   wire width 8 $15
7713   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7714   cell $or $16
7715     parameter \A_SIGNED 1'0
7716     parameter \A_WIDTH 4'1000
7717     parameter \B_SIGNED 1'0
7718     parameter \B_WIDTH 4'1000
7719     parameter \Y_WIDTH 4'1000
7720     connect \A \q
7721     connect \B \q_int
7722     connect \Y $15
7723   end
7724   process $group_3
7725     assign \qlq 8'00000000
7726     assign \qlq $15
7727     sync init
7728   end
7729 end
7730 attribute \generator "nMigen"
7731 attribute \nmigen.hierarchy "top.fumemdeps.dm5.ld_c"
7732 module \ld_c$24
7733   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7734   wire width 1 input 0 \rst
7735   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7736   wire width 1 input 1 \clk
7737   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7738   wire width 8 input 2 \s
7739   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7740   wire width 8 input 3 \r
7741   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7742   wire width 8 output 4 \qlq
7743   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7744   wire width 8 \q_int
7745   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7746   wire width 8 \q_int$next
7747   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7748   wire width 8 $1
7749   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7750   cell $not $2
7751     parameter \A_SIGNED 1'0
7752     parameter \A_WIDTH 4'1000
7753     parameter \Y_WIDTH 4'1000
7754     connect \A \r
7755     connect \Y $1
7756   end
7757   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7758   wire width 8 $3
7759   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7760   cell $and $4
7761     parameter \A_SIGNED 1'0
7762     parameter \A_WIDTH 4'1000
7763     parameter \B_SIGNED 1'0
7764     parameter \B_WIDTH 4'1000
7765     parameter \Y_WIDTH 4'1000
7766     connect \A \q_int
7767     connect \B $1
7768     connect \Y $3
7769   end
7770   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7771   wire width 8 $5
7772   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7773   cell $or $6
7774     parameter \A_SIGNED 1'0
7775     parameter \A_WIDTH 4'1000
7776     parameter \B_SIGNED 1'0
7777     parameter \B_WIDTH 4'1000
7778     parameter \Y_WIDTH 4'1000
7779     connect \A $3
7780     connect \B \s
7781     connect \Y $5
7782   end
7783   process $group_0
7784     assign \q_int$next \q_int
7785     assign \q_int$next $5
7786     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7787     switch \rst
7788       case 1'1
7789         assign \q_int$next 8'00000000
7790     end
7791     sync init
7792       update \q_int 8'00000000
7793     sync posedge \clk
7794       update \q_int \q_int$next
7795   end
7796   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7797   wire width 8 \q
7798   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7799   wire width 8 $7
7800   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7801   cell $not $8
7802     parameter \A_SIGNED 1'0
7803     parameter \A_WIDTH 4'1000
7804     parameter \Y_WIDTH 4'1000
7805     connect \A \r
7806     connect \Y $7
7807   end
7808   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7809   wire width 8 $9
7810   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7811   cell $and $10
7812     parameter \A_SIGNED 1'0
7813     parameter \A_WIDTH 4'1000
7814     parameter \B_SIGNED 1'0
7815     parameter \B_WIDTH 4'1000
7816     parameter \Y_WIDTH 4'1000
7817     connect \A \q_int
7818     connect \B $7
7819     connect \Y $9
7820   end
7821   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7822   wire width 8 $11
7823   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7824   cell $or $12
7825     parameter \A_SIGNED 1'0
7826     parameter \A_WIDTH 4'1000
7827     parameter \B_SIGNED 1'0
7828     parameter \B_WIDTH 4'1000
7829     parameter \Y_WIDTH 4'1000
7830     connect \A $9
7831     connect \B \s
7832     connect \Y $11
7833   end
7834   process $group_1
7835     assign \q 8'00000000
7836     assign \q $11
7837     sync init
7838   end
7839   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7840   wire width 8 \qn
7841   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7842   wire width 8 $13
7843   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7844   cell $not $14
7845     parameter \A_SIGNED 1'0
7846     parameter \A_WIDTH 4'1000
7847     parameter \Y_WIDTH 4'1000
7848     connect \A \q
7849     connect \Y $13
7850   end
7851   process $group_2
7852     assign \qn 8'00000000
7853     assign \qn $13
7854     sync init
7855   end
7856   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7857   wire width 8 $15
7858   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7859   cell $or $16
7860     parameter \A_SIGNED 1'0
7861     parameter \A_WIDTH 4'1000
7862     parameter \B_SIGNED 1'0
7863     parameter \B_WIDTH 4'1000
7864     parameter \Y_WIDTH 4'1000
7865     connect \A \q
7866     connect \B \q_int
7867     connect \Y $15
7868   end
7869   process $group_3
7870     assign \qlq 8'00000000
7871     assign \qlq $15
7872     sync init
7873   end
7874 end
7875 attribute \generator "nMigen"
7876 attribute \nmigen.hierarchy "top.fumemdeps.dm5"
7877 module \dm5
7878   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7879   wire width 1 input 0 \rst
7880   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7881   wire width 1 input 1 \clk
7882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
7883   wire width 8 output 2 \st_wait_o
7884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
7885   wire width 8 output 3 \ld_wait_o
7886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
7887   wire width 8 input 4 \issue_i
7888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
7889   wire width 8 input 5 \go_st_i
7890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
7891   wire width 8 input 6 \go_ld_i
7892   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
7893   wire width 8 input 7 \go_die_i
7894   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
7895   wire width 8 input 8 \st_pend_i
7896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
7897   wire width 8 input 9 \ld_pend_i
7898   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7899   wire width 8 \st_c_s
7900   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7901   wire width 8 \st_c_r
7902   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7903   wire width 8 \st_c_qlq
7904   cell \st_c$23 \st_c
7905     connect \rst \rst
7906     connect \clk \clk
7907     connect \s \st_c_s
7908     connect \r \st_c_r
7909     connect \qlq \st_c_qlq
7910   end
7911   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7912   wire width 8 \ld_c_s
7913   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7914   wire width 8 \ld_c_r
7915   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7916   wire width 8 \ld_c_qlq
7917   cell \ld_c$24 \ld_c
7918     connect \rst \rst
7919     connect \clk \clk
7920     connect \s \ld_c_s
7921     connect \r \ld_c_r
7922     connect \qlq \ld_c_qlq
7923   end
7924   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7925   wire width 8 $1
7926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7927   cell $and $2
7928     parameter \A_SIGNED 1'0
7929     parameter \A_WIDTH 4'1000
7930     parameter \B_SIGNED 1'0
7931     parameter \B_WIDTH 4'1000
7932     parameter \Y_WIDTH 4'1000
7933     connect \A \issue_i
7934     connect \B \st_pend_i
7935     connect \Y $1
7936   end
7937   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7938   wire width 9 $3
7939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7940   wire width 8 $4
7941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7942   cell $and $5
7943     parameter \A_SIGNED 1'0
7944     parameter \A_WIDTH 4'1000
7945     parameter \B_SIGNED 1'0
7946     parameter \B_WIDTH 4'1000
7947     parameter \Y_WIDTH 4'1000
7948     connect \A \issue_i
7949     connect \B \st_pend_i
7950     connect \Y $4
7951   end
7952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7953   wire width 9 $6
7954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7955   cell $and $7
7956     parameter \A_SIGNED 1'1
7957     parameter \A_WIDTH 4'1000
7958     parameter \B_SIGNED 1'1
7959     parameter \B_WIDTH 4'1000
7960     parameter \Y_WIDTH 4'1001
7961     connect \A $4
7962     connect \B 8'11011111
7963     connect \Y $6
7964   end
7965   connect $3 $6
7966   process $group_0
7967     assign \st_c_s 8'00000000
7968     assign \st_c_s $1
7969     assign \st_c_s $3 [7:0]
7970     sync init
7971   end
7972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7973   wire width 8 $8
7974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7975   cell $and $9
7976     parameter \A_SIGNED 1'0
7977     parameter \A_WIDTH 4'1000
7978     parameter \B_SIGNED 1'0
7979     parameter \B_WIDTH 4'1000
7980     parameter \Y_WIDTH 4'1000
7981     connect \A \issue_i
7982     connect \B \ld_pend_i
7983     connect \Y $8
7984   end
7985   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7986   wire width 9 $10
7987   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7988   wire width 8 $11
7989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7990   cell $and $12
7991     parameter \A_SIGNED 1'0
7992     parameter \A_WIDTH 4'1000
7993     parameter \B_SIGNED 1'0
7994     parameter \B_WIDTH 4'1000
7995     parameter \Y_WIDTH 4'1000
7996     connect \A \issue_i
7997     connect \B \ld_pend_i
7998     connect \Y $11
7999   end
8000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8001   wire width 9 $13
8002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8003   cell $and $14
8004     parameter \A_SIGNED 1'1
8005     parameter \A_WIDTH 4'1000
8006     parameter \B_SIGNED 1'1
8007     parameter \B_WIDTH 4'1000
8008     parameter \Y_WIDTH 4'1001
8009     connect \A $11
8010     connect \B 8'11011111
8011     connect \Y $13
8012   end
8013   connect $10 $13
8014   process $group_1
8015     assign \ld_c_s 8'00000000
8016     assign \ld_c_s $8
8017     assign \ld_c_s $10 [7:0]
8018     sync init
8019   end
8020   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8021   wire width 8 $15
8022   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8023   cell $or $16
8024     parameter \A_SIGNED 1'0
8025     parameter \A_WIDTH 4'1000
8026     parameter \B_SIGNED 1'0
8027     parameter \B_WIDTH 4'1000
8028     parameter \Y_WIDTH 4'1000
8029     connect \A \go_ld_i
8030     connect \B \go_die_i
8031     connect \Y $15
8032   end
8033   process $group_2
8034     assign \ld_c_r 8'11111111
8035     assign \ld_c_r $15
8036     sync init
8037   end
8038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8039   wire width 8 $17
8040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8041   cell $or $18
8042     parameter \A_SIGNED 1'0
8043     parameter \A_WIDTH 4'1000
8044     parameter \B_SIGNED 1'0
8045     parameter \B_WIDTH 4'1000
8046     parameter \Y_WIDTH 4'1000
8047     connect \A \go_st_i
8048     connect \B \go_die_i
8049     connect \Y $17
8050   end
8051   process $group_3
8052     assign \st_c_r 8'11111111
8053     assign \st_c_r $17
8054     sync init
8055   end
8056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8057   wire width 8 $19
8058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8059   cell $not $20
8060     parameter \A_SIGNED 1'0
8061     parameter \A_WIDTH 4'1000
8062     parameter \Y_WIDTH 4'1000
8063     connect \A \issue_i
8064     connect \Y $19
8065   end
8066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8067   wire width 8 $21
8068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8069   cell $and $22
8070     parameter \A_SIGNED 1'0
8071     parameter \A_WIDTH 4'1000
8072     parameter \B_SIGNED 1'0
8073     parameter \B_WIDTH 4'1000
8074     parameter \Y_WIDTH 4'1000
8075     connect \A \st_c_qlq
8076     connect \B $19
8077     connect \Y $21
8078   end
8079   process $group_4
8080     assign \st_wait_o 8'00000000
8081     assign \st_wait_o $21
8082     sync init
8083   end
8084   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8085   wire width 8 $23
8086   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8087   cell $not $24
8088     parameter \A_SIGNED 1'0
8089     parameter \A_WIDTH 4'1000
8090     parameter \Y_WIDTH 4'1000
8091     connect \A \issue_i
8092     connect \Y $23
8093   end
8094   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8095   wire width 8 $25
8096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8097   cell $and $26
8098     parameter \A_SIGNED 1'0
8099     parameter \A_WIDTH 4'1000
8100     parameter \B_SIGNED 1'0
8101     parameter \B_WIDTH 4'1000
8102     parameter \Y_WIDTH 4'1000
8103     connect \A \ld_c_qlq
8104     connect \B $23
8105     connect \Y $25
8106   end
8107   process $group_5
8108     assign \ld_wait_o 8'00000000
8109     assign \ld_wait_o $25
8110     sync init
8111   end
8112 end
8113 attribute \generator "nMigen"
8114 attribute \nmigen.hierarchy "top.fumemdeps.dm6.st_c"
8115 module \st_c$25
8116   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8117   wire width 1 input 0 \rst
8118   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8119   wire width 1 input 1 \clk
8120   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8121   wire width 8 input 2 \s
8122   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8123   wire width 8 input 3 \r
8124   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8125   wire width 8 output 4 \qlq
8126   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8127   wire width 8 \q_int
8128   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8129   wire width 8 \q_int$next
8130   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8131   wire width 8 $1
8132   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8133   cell $not $2
8134     parameter \A_SIGNED 1'0
8135     parameter \A_WIDTH 4'1000
8136     parameter \Y_WIDTH 4'1000
8137     connect \A \r
8138     connect \Y $1
8139   end
8140   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8141   wire width 8 $3
8142   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8143   cell $and $4
8144     parameter \A_SIGNED 1'0
8145     parameter \A_WIDTH 4'1000
8146     parameter \B_SIGNED 1'0
8147     parameter \B_WIDTH 4'1000
8148     parameter \Y_WIDTH 4'1000
8149     connect \A \q_int
8150     connect \B $1
8151     connect \Y $3
8152   end
8153   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8154   wire width 8 $5
8155   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8156   cell $or $6
8157     parameter \A_SIGNED 1'0
8158     parameter \A_WIDTH 4'1000
8159     parameter \B_SIGNED 1'0
8160     parameter \B_WIDTH 4'1000
8161     parameter \Y_WIDTH 4'1000
8162     connect \A $3
8163     connect \B \s
8164     connect \Y $5
8165   end
8166   process $group_0
8167     assign \q_int$next \q_int
8168     assign \q_int$next $5
8169     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8170     switch \rst
8171       case 1'1
8172         assign \q_int$next 8'00000000
8173     end
8174     sync init
8175       update \q_int 8'00000000
8176     sync posedge \clk
8177       update \q_int \q_int$next
8178   end
8179   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8180   wire width 8 \q
8181   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8182   wire width 8 $7
8183   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8184   cell $not $8
8185     parameter \A_SIGNED 1'0
8186     parameter \A_WIDTH 4'1000
8187     parameter \Y_WIDTH 4'1000
8188     connect \A \r
8189     connect \Y $7
8190   end
8191   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8192   wire width 8 $9
8193   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8194   cell $and $10
8195     parameter \A_SIGNED 1'0
8196     parameter \A_WIDTH 4'1000
8197     parameter \B_SIGNED 1'0
8198     parameter \B_WIDTH 4'1000
8199     parameter \Y_WIDTH 4'1000
8200     connect \A \q_int
8201     connect \B $7
8202     connect \Y $9
8203   end
8204   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8205   wire width 8 $11
8206   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8207   cell $or $12
8208     parameter \A_SIGNED 1'0
8209     parameter \A_WIDTH 4'1000
8210     parameter \B_SIGNED 1'0
8211     parameter \B_WIDTH 4'1000
8212     parameter \Y_WIDTH 4'1000
8213     connect \A $9
8214     connect \B \s
8215     connect \Y $11
8216   end
8217   process $group_1
8218     assign \q 8'00000000
8219     assign \q $11
8220     sync init
8221   end
8222   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8223   wire width 8 \qn
8224   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8225   wire width 8 $13
8226   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8227   cell $not $14
8228     parameter \A_SIGNED 1'0
8229     parameter \A_WIDTH 4'1000
8230     parameter \Y_WIDTH 4'1000
8231     connect \A \q
8232     connect \Y $13
8233   end
8234   process $group_2
8235     assign \qn 8'00000000
8236     assign \qn $13
8237     sync init
8238   end
8239   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8240   wire width 8 $15
8241   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8242   cell $or $16
8243     parameter \A_SIGNED 1'0
8244     parameter \A_WIDTH 4'1000
8245     parameter \B_SIGNED 1'0
8246     parameter \B_WIDTH 4'1000
8247     parameter \Y_WIDTH 4'1000
8248     connect \A \q
8249     connect \B \q_int
8250     connect \Y $15
8251   end
8252   process $group_3
8253     assign \qlq 8'00000000
8254     assign \qlq $15
8255     sync init
8256   end
8257 end
8258 attribute \generator "nMigen"
8259 attribute \nmigen.hierarchy "top.fumemdeps.dm6.ld_c"
8260 module \ld_c$26
8261   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8262   wire width 1 input 0 \rst
8263   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8264   wire width 1 input 1 \clk
8265   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8266   wire width 8 input 2 \s
8267   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8268   wire width 8 input 3 \r
8269   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8270   wire width 8 output 4 \qlq
8271   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8272   wire width 8 \q_int
8273   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8274   wire width 8 \q_int$next
8275   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8276   wire width 8 $1
8277   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8278   cell $not $2
8279     parameter \A_SIGNED 1'0
8280     parameter \A_WIDTH 4'1000
8281     parameter \Y_WIDTH 4'1000
8282     connect \A \r
8283     connect \Y $1
8284   end
8285   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8286   wire width 8 $3
8287   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8288   cell $and $4
8289     parameter \A_SIGNED 1'0
8290     parameter \A_WIDTH 4'1000
8291     parameter \B_SIGNED 1'0
8292     parameter \B_WIDTH 4'1000
8293     parameter \Y_WIDTH 4'1000
8294     connect \A \q_int
8295     connect \B $1
8296     connect \Y $3
8297   end
8298   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8299   wire width 8 $5
8300   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8301   cell $or $6
8302     parameter \A_SIGNED 1'0
8303     parameter \A_WIDTH 4'1000
8304     parameter \B_SIGNED 1'0
8305     parameter \B_WIDTH 4'1000
8306     parameter \Y_WIDTH 4'1000
8307     connect \A $3
8308     connect \B \s
8309     connect \Y $5
8310   end
8311   process $group_0
8312     assign \q_int$next \q_int
8313     assign \q_int$next $5
8314     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8315     switch \rst
8316       case 1'1
8317         assign \q_int$next 8'00000000
8318     end
8319     sync init
8320       update \q_int 8'00000000
8321     sync posedge \clk
8322       update \q_int \q_int$next
8323   end
8324   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8325   wire width 8 \q
8326   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8327   wire width 8 $7
8328   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8329   cell $not $8
8330     parameter \A_SIGNED 1'0
8331     parameter \A_WIDTH 4'1000
8332     parameter \Y_WIDTH 4'1000
8333     connect \A \r
8334     connect \Y $7
8335   end
8336   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8337   wire width 8 $9
8338   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8339   cell $and $10
8340     parameter \A_SIGNED 1'0
8341     parameter \A_WIDTH 4'1000
8342     parameter \B_SIGNED 1'0
8343     parameter \B_WIDTH 4'1000
8344     parameter \Y_WIDTH 4'1000
8345     connect \A \q_int
8346     connect \B $7
8347     connect \Y $9
8348   end
8349   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8350   wire width 8 $11
8351   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8352   cell $or $12
8353     parameter \A_SIGNED 1'0
8354     parameter \A_WIDTH 4'1000
8355     parameter \B_SIGNED 1'0
8356     parameter \B_WIDTH 4'1000
8357     parameter \Y_WIDTH 4'1000
8358     connect \A $9
8359     connect \B \s
8360     connect \Y $11
8361   end
8362   process $group_1
8363     assign \q 8'00000000
8364     assign \q $11
8365     sync init
8366   end
8367   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8368   wire width 8 \qn
8369   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8370   wire width 8 $13
8371   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8372   cell $not $14
8373     parameter \A_SIGNED 1'0
8374     parameter \A_WIDTH 4'1000
8375     parameter \Y_WIDTH 4'1000
8376     connect \A \q
8377     connect \Y $13
8378   end
8379   process $group_2
8380     assign \qn 8'00000000
8381     assign \qn $13
8382     sync init
8383   end
8384   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8385   wire width 8 $15
8386   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8387   cell $or $16
8388     parameter \A_SIGNED 1'0
8389     parameter \A_WIDTH 4'1000
8390     parameter \B_SIGNED 1'0
8391     parameter \B_WIDTH 4'1000
8392     parameter \Y_WIDTH 4'1000
8393     connect \A \q
8394     connect \B \q_int
8395     connect \Y $15
8396   end
8397   process $group_3
8398     assign \qlq 8'00000000
8399     assign \qlq $15
8400     sync init
8401   end
8402 end
8403 attribute \generator "nMigen"
8404 attribute \nmigen.hierarchy "top.fumemdeps.dm6"
8405 module \dm6
8406   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8407   wire width 1 input 0 \rst
8408   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8409   wire width 1 input 1 \clk
8410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
8411   wire width 8 output 2 \st_wait_o
8412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
8413   wire width 8 output 3 \ld_wait_o
8414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
8415   wire width 8 input 4 \issue_i
8416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
8417   wire width 8 input 5 \go_st_i
8418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
8419   wire width 8 input 6 \go_ld_i
8420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
8421   wire width 8 input 7 \go_die_i
8422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
8423   wire width 8 input 8 \st_pend_i
8424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
8425   wire width 8 input 9 \ld_pend_i
8426   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8427   wire width 8 \st_c_s
8428   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8429   wire width 8 \st_c_r
8430   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8431   wire width 8 \st_c_qlq
8432   cell \st_c$25 \st_c
8433     connect \rst \rst
8434     connect \clk \clk
8435     connect \s \st_c_s
8436     connect \r \st_c_r
8437     connect \qlq \st_c_qlq
8438   end
8439   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8440   wire width 8 \ld_c_s
8441   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8442   wire width 8 \ld_c_r
8443   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8444   wire width 8 \ld_c_qlq
8445   cell \ld_c$26 \ld_c
8446     connect \rst \rst
8447     connect \clk \clk
8448     connect \s \ld_c_s
8449     connect \r \ld_c_r
8450     connect \qlq \ld_c_qlq
8451   end
8452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8453   wire width 8 $1
8454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8455   cell $and $2
8456     parameter \A_SIGNED 1'0
8457     parameter \A_WIDTH 4'1000
8458     parameter \B_SIGNED 1'0
8459     parameter \B_WIDTH 4'1000
8460     parameter \Y_WIDTH 4'1000
8461     connect \A \issue_i
8462     connect \B \st_pend_i
8463     connect \Y $1
8464   end
8465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8466   wire width 9 $3
8467   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8468   wire width 8 $4
8469   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8470   cell $and $5
8471     parameter \A_SIGNED 1'0
8472     parameter \A_WIDTH 4'1000
8473     parameter \B_SIGNED 1'0
8474     parameter \B_WIDTH 4'1000
8475     parameter \Y_WIDTH 4'1000
8476     connect \A \issue_i
8477     connect \B \st_pend_i
8478     connect \Y $4
8479   end
8480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8481   wire width 9 $6
8482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8483   cell $and $7
8484     parameter \A_SIGNED 1'1
8485     parameter \A_WIDTH 4'1000
8486     parameter \B_SIGNED 1'1
8487     parameter \B_WIDTH 4'1000
8488     parameter \Y_WIDTH 4'1001
8489     connect \A $4
8490     connect \B 8'10111111
8491     connect \Y $6
8492   end
8493   connect $3 $6
8494   process $group_0
8495     assign \st_c_s 8'00000000
8496     assign \st_c_s $1
8497     assign \st_c_s $3 [7:0]
8498     sync init
8499   end
8500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
8501   wire width 8 $8
8502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
8503   cell $and $9
8504     parameter \A_SIGNED 1'0
8505     parameter \A_WIDTH 4'1000
8506     parameter \B_SIGNED 1'0
8507     parameter \B_WIDTH 4'1000
8508     parameter \Y_WIDTH 4'1000
8509     connect \A \issue_i
8510     connect \B \ld_pend_i
8511     connect \Y $8
8512   end
8513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8514   wire width 9 $10
8515   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8516   wire width 8 $11
8517   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8518   cell $and $12
8519     parameter \A_SIGNED 1'0
8520     parameter \A_WIDTH 4'1000
8521     parameter \B_SIGNED 1'0
8522     parameter \B_WIDTH 4'1000
8523     parameter \Y_WIDTH 4'1000
8524     connect \A \issue_i
8525     connect \B \ld_pend_i
8526     connect \Y $11
8527   end
8528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8529   wire width 9 $13
8530   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8531   cell $and $14
8532     parameter \A_SIGNED 1'1
8533     parameter \A_WIDTH 4'1000
8534     parameter \B_SIGNED 1'1
8535     parameter \B_WIDTH 4'1000
8536     parameter \Y_WIDTH 4'1001
8537     connect \A $11
8538     connect \B 8'10111111
8539     connect \Y $13
8540   end
8541   connect $10 $13
8542   process $group_1
8543     assign \ld_c_s 8'00000000
8544     assign \ld_c_s $8
8545     assign \ld_c_s $10 [7:0]
8546     sync init
8547   end
8548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8549   wire width 8 $15
8550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8551   cell $or $16
8552     parameter \A_SIGNED 1'0
8553     parameter \A_WIDTH 4'1000
8554     parameter \B_SIGNED 1'0
8555     parameter \B_WIDTH 4'1000
8556     parameter \Y_WIDTH 4'1000
8557     connect \A \go_ld_i
8558     connect \B \go_die_i
8559     connect \Y $15
8560   end
8561   process $group_2
8562     assign \ld_c_r 8'11111111
8563     assign \ld_c_r $15
8564     sync init
8565   end
8566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8567   wire width 8 $17
8568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8569   cell $or $18
8570     parameter \A_SIGNED 1'0
8571     parameter \A_WIDTH 4'1000
8572     parameter \B_SIGNED 1'0
8573     parameter \B_WIDTH 4'1000
8574     parameter \Y_WIDTH 4'1000
8575     connect \A \go_st_i
8576     connect \B \go_die_i
8577     connect \Y $17
8578   end
8579   process $group_3
8580     assign \st_c_r 8'11111111
8581     assign \st_c_r $17
8582     sync init
8583   end
8584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8585   wire width 8 $19
8586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8587   cell $not $20
8588     parameter \A_SIGNED 1'0
8589     parameter \A_WIDTH 4'1000
8590     parameter \Y_WIDTH 4'1000
8591     connect \A \issue_i
8592     connect \Y $19
8593   end
8594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8595   wire width 8 $21
8596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8597   cell $and $22
8598     parameter \A_SIGNED 1'0
8599     parameter \A_WIDTH 4'1000
8600     parameter \B_SIGNED 1'0
8601     parameter \B_WIDTH 4'1000
8602     parameter \Y_WIDTH 4'1000
8603     connect \A \st_c_qlq
8604     connect \B $19
8605     connect \Y $21
8606   end
8607   process $group_4
8608     assign \st_wait_o 8'00000000
8609     assign \st_wait_o $21
8610     sync init
8611   end
8612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8613   wire width 8 $23
8614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8615   cell $not $24
8616     parameter \A_SIGNED 1'0
8617     parameter \A_WIDTH 4'1000
8618     parameter \Y_WIDTH 4'1000
8619     connect \A \issue_i
8620     connect \Y $23
8621   end
8622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8623   wire width 8 $25
8624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8625   cell $and $26
8626     parameter \A_SIGNED 1'0
8627     parameter \A_WIDTH 4'1000
8628     parameter \B_SIGNED 1'0
8629     parameter \B_WIDTH 4'1000
8630     parameter \Y_WIDTH 4'1000
8631     connect \A \ld_c_qlq
8632     connect \B $23
8633     connect \Y $25
8634   end
8635   process $group_5
8636     assign \ld_wait_o 8'00000000
8637     assign \ld_wait_o $25
8638     sync init
8639   end
8640 end
8641 attribute \generator "nMigen"
8642 attribute \nmigen.hierarchy "top.fumemdeps.dm7.st_c"
8643 module \st_c$27
8644   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8645   wire width 1 input 0 \rst
8646   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8647   wire width 1 input 1 \clk
8648   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8649   wire width 8 input 2 \s
8650   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8651   wire width 8 input 3 \r
8652   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8653   wire width 8 output 4 \qlq
8654   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8655   wire width 8 \q_int
8656   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8657   wire width 8 \q_int$next
8658   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8659   wire width 8 $1
8660   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8661   cell $not $2
8662     parameter \A_SIGNED 1'0
8663     parameter \A_WIDTH 4'1000
8664     parameter \Y_WIDTH 4'1000
8665     connect \A \r
8666     connect \Y $1
8667   end
8668   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8669   wire width 8 $3
8670   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8671   cell $and $4
8672     parameter \A_SIGNED 1'0
8673     parameter \A_WIDTH 4'1000
8674     parameter \B_SIGNED 1'0
8675     parameter \B_WIDTH 4'1000
8676     parameter \Y_WIDTH 4'1000
8677     connect \A \q_int
8678     connect \B $1
8679     connect \Y $3
8680   end
8681   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8682   wire width 8 $5
8683   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8684   cell $or $6
8685     parameter \A_SIGNED 1'0
8686     parameter \A_WIDTH 4'1000
8687     parameter \B_SIGNED 1'0
8688     parameter \B_WIDTH 4'1000
8689     parameter \Y_WIDTH 4'1000
8690     connect \A $3
8691     connect \B \s
8692     connect \Y $5
8693   end
8694   process $group_0
8695     assign \q_int$next \q_int
8696     assign \q_int$next $5
8697     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8698     switch \rst
8699       case 1'1
8700         assign \q_int$next 8'00000000
8701     end
8702     sync init
8703       update \q_int 8'00000000
8704     sync posedge \clk
8705       update \q_int \q_int$next
8706   end
8707   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8708   wire width 8 \q
8709   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8710   wire width 8 $7
8711   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8712   cell $not $8
8713     parameter \A_SIGNED 1'0
8714     parameter \A_WIDTH 4'1000
8715     parameter \Y_WIDTH 4'1000
8716     connect \A \r
8717     connect \Y $7
8718   end
8719   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8720   wire width 8 $9
8721   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8722   cell $and $10
8723     parameter \A_SIGNED 1'0
8724     parameter \A_WIDTH 4'1000
8725     parameter \B_SIGNED 1'0
8726     parameter \B_WIDTH 4'1000
8727     parameter \Y_WIDTH 4'1000
8728     connect \A \q_int
8729     connect \B $7
8730     connect \Y $9
8731   end
8732   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8733   wire width 8 $11
8734   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8735   cell $or $12
8736     parameter \A_SIGNED 1'0
8737     parameter \A_WIDTH 4'1000
8738     parameter \B_SIGNED 1'0
8739     parameter \B_WIDTH 4'1000
8740     parameter \Y_WIDTH 4'1000
8741     connect \A $9
8742     connect \B \s
8743     connect \Y $11
8744   end
8745   process $group_1
8746     assign \q 8'00000000
8747     assign \q $11
8748     sync init
8749   end
8750   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8751   wire width 8 \qn
8752   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8753   wire width 8 $13
8754   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8755   cell $not $14
8756     parameter \A_SIGNED 1'0
8757     parameter \A_WIDTH 4'1000
8758     parameter \Y_WIDTH 4'1000
8759     connect \A \q
8760     connect \Y $13
8761   end
8762   process $group_2
8763     assign \qn 8'00000000
8764     assign \qn $13
8765     sync init
8766   end
8767   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8768   wire width 8 $15
8769   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8770   cell $or $16
8771     parameter \A_SIGNED 1'0
8772     parameter \A_WIDTH 4'1000
8773     parameter \B_SIGNED 1'0
8774     parameter \B_WIDTH 4'1000
8775     parameter \Y_WIDTH 4'1000
8776     connect \A \q
8777     connect \B \q_int
8778     connect \Y $15
8779   end
8780   process $group_3
8781     assign \qlq 8'00000000
8782     assign \qlq $15
8783     sync init
8784   end
8785 end
8786 attribute \generator "nMigen"
8787 attribute \nmigen.hierarchy "top.fumemdeps.dm7.ld_c"
8788 module \ld_c$28
8789   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8790   wire width 1 input 0 \rst
8791   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8792   wire width 1 input 1 \clk
8793   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8794   wire width 8 input 2 \s
8795   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8796   wire width 8 input 3 \r
8797   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8798   wire width 8 output 4 \qlq
8799   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8800   wire width 8 \q_int
8801   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8802   wire width 8 \q_int$next
8803   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8804   wire width 8 $1
8805   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8806   cell $not $2
8807     parameter \A_SIGNED 1'0
8808     parameter \A_WIDTH 4'1000
8809     parameter \Y_WIDTH 4'1000
8810     connect \A \r
8811     connect \Y $1
8812   end
8813   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8814   wire width 8 $3
8815   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8816   cell $and $4
8817     parameter \A_SIGNED 1'0
8818     parameter \A_WIDTH 4'1000
8819     parameter \B_SIGNED 1'0
8820     parameter \B_WIDTH 4'1000
8821     parameter \Y_WIDTH 4'1000
8822     connect \A \q_int
8823     connect \B $1
8824     connect \Y $3
8825   end
8826   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8827   wire width 8 $5
8828   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8829   cell $or $6
8830     parameter \A_SIGNED 1'0
8831     parameter \A_WIDTH 4'1000
8832     parameter \B_SIGNED 1'0
8833     parameter \B_WIDTH 4'1000
8834     parameter \Y_WIDTH 4'1000
8835     connect \A $3
8836     connect \B \s
8837     connect \Y $5
8838   end
8839   process $group_0
8840     assign \q_int$next \q_int
8841     assign \q_int$next $5
8842     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8843     switch \rst
8844       case 1'1
8845         assign \q_int$next 8'00000000
8846     end
8847     sync init
8848       update \q_int 8'00000000
8849     sync posedge \clk
8850       update \q_int \q_int$next
8851   end
8852   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8853   wire width 8 \q
8854   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8855   wire width 8 $7
8856   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8857   cell $not $8
8858     parameter \A_SIGNED 1'0
8859     parameter \A_WIDTH 4'1000
8860     parameter \Y_WIDTH 4'1000
8861     connect \A \r
8862     connect \Y $7
8863   end
8864   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8865   wire width 8 $9
8866   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8867   cell $and $10
8868     parameter \A_SIGNED 1'0
8869     parameter \A_WIDTH 4'1000
8870     parameter \B_SIGNED 1'0
8871     parameter \B_WIDTH 4'1000
8872     parameter \Y_WIDTH 4'1000
8873     connect \A \q_int
8874     connect \B $7
8875     connect \Y $9
8876   end
8877   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8878   wire width 8 $11
8879   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8880   cell $or $12
8881     parameter \A_SIGNED 1'0
8882     parameter \A_WIDTH 4'1000
8883     parameter \B_SIGNED 1'0
8884     parameter \B_WIDTH 4'1000
8885     parameter \Y_WIDTH 4'1000
8886     connect \A $9
8887     connect \B \s
8888     connect \Y $11
8889   end
8890   process $group_1
8891     assign \q 8'00000000
8892     assign \q $11
8893     sync init
8894   end
8895   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8896   wire width 8 \qn
8897   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8898   wire width 8 $13
8899   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8900   cell $not $14
8901     parameter \A_SIGNED 1'0
8902     parameter \A_WIDTH 4'1000
8903     parameter \Y_WIDTH 4'1000
8904     connect \A \q
8905     connect \Y $13
8906   end
8907   process $group_2
8908     assign \qn 8'00000000
8909     assign \qn $13
8910     sync init
8911   end
8912   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8913   wire width 8 $15
8914   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8915   cell $or $16
8916     parameter \A_SIGNED 1'0
8917     parameter \A_WIDTH 4'1000
8918     parameter \B_SIGNED 1'0
8919     parameter \B_WIDTH 4'1000
8920     parameter \Y_WIDTH 4'1000
8921     connect \A \q
8922     connect \B \q_int
8923     connect \Y $15
8924   end
8925   process $group_3
8926     assign \qlq 8'00000000
8927     assign \qlq $15
8928     sync init
8929   end
8930 end
8931 attribute \generator "nMigen"
8932 attribute \nmigen.hierarchy "top.fumemdeps.dm7"
8933 module \dm7
8934   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8935   wire width 1 input 0 \rst
8936   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8937   wire width 1 input 1 \clk
8938   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
8939   wire width 8 output 2 \st_wait_o
8940   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
8941   wire width 8 output 3 \ld_wait_o
8942   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
8943   wire width 8 input 4 \issue_i
8944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
8945   wire width 8 input 5 \go_st_i
8946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
8947   wire width 8 input 6 \go_ld_i
8948   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
8949   wire width 8 input 7 \go_die_i
8950   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
8951   wire width 8 input 8 \st_pend_i
8952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
8953   wire width 8 input 9 \ld_pend_i
8954   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8955   wire width 8 \st_c_s
8956   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8957   wire width 8 \st_c_r
8958   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8959   wire width 8 \st_c_qlq
8960   cell \st_c$27 \st_c
8961     connect \rst \rst
8962     connect \clk \clk
8963     connect \s \st_c_s
8964     connect \r \st_c_r
8965     connect \qlq \st_c_qlq
8966   end
8967   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8968   wire width 8 \ld_c_s
8969   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8970   wire width 8 \ld_c_r
8971   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8972   wire width 8 \ld_c_qlq
8973   cell \ld_c$28 \ld_c
8974     connect \rst \rst
8975     connect \clk \clk
8976     connect \s \ld_c_s
8977     connect \r \ld_c_r
8978     connect \qlq \ld_c_qlq
8979   end
8980   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8981   wire width 8 $1
8982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8983   cell $and $2
8984     parameter \A_SIGNED 1'0
8985     parameter \A_WIDTH 4'1000
8986     parameter \B_SIGNED 1'0
8987     parameter \B_WIDTH 4'1000
8988     parameter \Y_WIDTH 4'1000
8989     connect \A \issue_i
8990     connect \B \st_pend_i
8991     connect \Y $1
8992   end
8993   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8994   wire width 9 $3
8995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8996   wire width 8 $4
8997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8998   cell $and $5
8999     parameter \A_SIGNED 1'0
9000     parameter \A_WIDTH 4'1000
9001     parameter \B_SIGNED 1'0
9002     parameter \B_WIDTH 4'1000
9003     parameter \Y_WIDTH 4'1000
9004     connect \A \issue_i
9005     connect \B \st_pend_i
9006     connect \Y $4
9007   end
9008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
9009   wire width 9 $6
9010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
9011   cell $and $7
9012     parameter \A_SIGNED 1'1
9013     parameter \A_WIDTH 4'1000
9014     parameter \B_SIGNED 1'1
9015     parameter \B_WIDTH 4'1000
9016     parameter \Y_WIDTH 4'1001
9017     connect \A $4
9018     connect \B 8'01111111
9019     connect \Y $6
9020   end
9021   connect $3 $6
9022   process $group_0
9023     assign \st_c_s 8'00000000
9024     assign \st_c_s $1
9025     assign \st_c_s $3 [7:0]
9026     sync init
9027   end
9028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
9029   wire width 8 $8
9030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
9031   cell $and $9
9032     parameter \A_SIGNED 1'0
9033     parameter \A_WIDTH 4'1000
9034     parameter \B_SIGNED 1'0
9035     parameter \B_WIDTH 4'1000
9036     parameter \Y_WIDTH 4'1000
9037     connect \A \issue_i
9038     connect \B \ld_pend_i
9039     connect \Y $8
9040   end
9041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9042   wire width 9 $10
9043   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9044   wire width 8 $11
9045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9046   cell $and $12
9047     parameter \A_SIGNED 1'0
9048     parameter \A_WIDTH 4'1000
9049     parameter \B_SIGNED 1'0
9050     parameter \B_WIDTH 4'1000
9051     parameter \Y_WIDTH 4'1000
9052     connect \A \issue_i
9053     connect \B \ld_pend_i
9054     connect \Y $11
9055   end
9056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9057   wire width 9 $13
9058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9059   cell $and $14
9060     parameter \A_SIGNED 1'1
9061     parameter \A_WIDTH 4'1000
9062     parameter \B_SIGNED 1'1
9063     parameter \B_WIDTH 4'1000
9064     parameter \Y_WIDTH 4'1001
9065     connect \A $11
9066     connect \B 8'01111111
9067     connect \Y $13
9068   end
9069   connect $10 $13
9070   process $group_1
9071     assign \ld_c_s 8'00000000
9072     assign \ld_c_s $8
9073     assign \ld_c_s $10 [7:0]
9074     sync init
9075   end
9076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
9077   wire width 8 $15
9078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
9079   cell $or $16
9080     parameter \A_SIGNED 1'0
9081     parameter \A_WIDTH 4'1000
9082     parameter \B_SIGNED 1'0
9083     parameter \B_WIDTH 4'1000
9084     parameter \Y_WIDTH 4'1000
9085     connect \A \go_ld_i
9086     connect \B \go_die_i
9087     connect \Y $15
9088   end
9089   process $group_2
9090     assign \ld_c_r 8'11111111
9091     assign \ld_c_r $15
9092     sync init
9093   end
9094   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
9095   wire width 8 $17
9096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
9097   cell $or $18
9098     parameter \A_SIGNED 1'0
9099     parameter \A_WIDTH 4'1000
9100     parameter \B_SIGNED 1'0
9101     parameter \B_WIDTH 4'1000
9102     parameter \Y_WIDTH 4'1000
9103     connect \A \go_st_i
9104     connect \B \go_die_i
9105     connect \Y $17
9106   end
9107   process $group_3
9108     assign \st_c_r 8'11111111
9109     assign \st_c_r $17
9110     sync init
9111   end
9112   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9113   wire width 8 $19
9114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9115   cell $not $20
9116     parameter \A_SIGNED 1'0
9117     parameter \A_WIDTH 4'1000
9118     parameter \Y_WIDTH 4'1000
9119     connect \A \issue_i
9120     connect \Y $19
9121   end
9122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9123   wire width 8 $21
9124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9125   cell $and $22
9126     parameter \A_SIGNED 1'0
9127     parameter \A_WIDTH 4'1000
9128     parameter \B_SIGNED 1'0
9129     parameter \B_WIDTH 4'1000
9130     parameter \Y_WIDTH 4'1000
9131     connect \A \st_c_qlq
9132     connect \B $19
9133     connect \Y $21
9134   end
9135   process $group_4
9136     assign \st_wait_o 8'00000000
9137     assign \st_wait_o $21
9138     sync init
9139   end
9140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9141   wire width 8 $23
9142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9143   cell $not $24
9144     parameter \A_SIGNED 1'0
9145     parameter \A_WIDTH 4'1000
9146     parameter \Y_WIDTH 4'1000
9147     connect \A \issue_i
9148     connect \Y $23
9149   end
9150   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9151   wire width 8 $25
9152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9153   cell $and $26
9154     parameter \A_SIGNED 1'0
9155     parameter \A_WIDTH 4'1000
9156     parameter \B_SIGNED 1'0
9157     parameter \B_WIDTH 4'1000
9158     parameter \Y_WIDTH 4'1000
9159     connect \A \ld_c_qlq
9160     connect \B $23
9161     connect \Y $25
9162   end
9163   process $group_5
9164     assign \ld_wait_o 8'00000000
9165     assign \ld_wait_o $25
9166     sync init
9167   end
9168 end
9169 attribute \generator "nMigen"
9170 attribute \nmigen.hierarchy "top.fumemdeps.fur_x0"
9171 module \fur_x0
9172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9173   wire width 1 output 0 \storable_o
9174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9175   wire width 1 output 1 \loadable_o
9176   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9177   wire width 8 input 2 \st_pend_i
9178   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9179   wire width 8 input 3 \ld_pend_i
9180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9181   wire width 1 $1
9182   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9183   wire width 1 $2
9184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9185   cell $reduce_bool $3
9186     parameter \A_SIGNED 1'0
9187     parameter \A_WIDTH 4'1000
9188     parameter \Y_WIDTH 1'1
9189     connect \A \ld_pend_i
9190     connect \Y $2
9191   end
9192   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9193   cell $not $4
9194     parameter \A_SIGNED 1'0
9195     parameter \A_WIDTH 1'1
9196     parameter \Y_WIDTH 1'1
9197     connect \A $2
9198     connect \Y $1
9199   end
9200   process $group_0
9201     assign \storable_o 1'0
9202     assign \storable_o $1
9203     sync init
9204   end
9205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9206   wire width 1 $5
9207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9208   wire width 1 $6
9209   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9210   cell $reduce_bool $7
9211     parameter \A_SIGNED 1'0
9212     parameter \A_WIDTH 4'1000
9213     parameter \Y_WIDTH 1'1
9214     connect \A \st_pend_i
9215     connect \Y $6
9216   end
9217   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9218   cell $not $8
9219     parameter \A_SIGNED 1'0
9220     parameter \A_WIDTH 1'1
9221     parameter \Y_WIDTH 1'1
9222     connect \A $6
9223     connect \Y $5
9224   end
9225   process $group_1
9226     assign \loadable_o 1'0
9227     assign \loadable_o $5
9228     sync init
9229   end
9230 end
9231 attribute \generator "nMigen"
9232 attribute \nmigen.hierarchy "top.fumemdeps.fur_x1"
9233 module \fur_x1
9234   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9235   wire width 1 output 0 \storable_o
9236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9237   wire width 1 output 1 \loadable_o
9238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9239   wire width 8 input 2 \st_pend_i
9240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9241   wire width 8 input 3 \ld_pend_i
9242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9243   wire width 1 $1
9244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9245   wire width 1 $2
9246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9247   cell $reduce_bool $3
9248     parameter \A_SIGNED 1'0
9249     parameter \A_WIDTH 4'1000
9250     parameter \Y_WIDTH 1'1
9251     connect \A \ld_pend_i
9252     connect \Y $2
9253   end
9254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9255   cell $not $4
9256     parameter \A_SIGNED 1'0
9257     parameter \A_WIDTH 1'1
9258     parameter \Y_WIDTH 1'1
9259     connect \A $2
9260     connect \Y $1
9261   end
9262   process $group_0
9263     assign \storable_o 1'0
9264     assign \storable_o $1
9265     sync init
9266   end
9267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9268   wire width 1 $5
9269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9270   wire width 1 $6
9271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9272   cell $reduce_bool $7
9273     parameter \A_SIGNED 1'0
9274     parameter \A_WIDTH 4'1000
9275     parameter \Y_WIDTH 1'1
9276     connect \A \st_pend_i
9277     connect \Y $6
9278   end
9279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9280   cell $not $8
9281     parameter \A_SIGNED 1'0
9282     parameter \A_WIDTH 1'1
9283     parameter \Y_WIDTH 1'1
9284     connect \A $6
9285     connect \Y $5
9286   end
9287   process $group_1
9288     assign \loadable_o 1'0
9289     assign \loadable_o $5
9290     sync init
9291   end
9292 end
9293 attribute \generator "nMigen"
9294 attribute \nmigen.hierarchy "top.fumemdeps.fur_x2"
9295 module \fur_x2
9296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9297   wire width 1 output 0 \storable_o
9298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9299   wire width 1 output 1 \loadable_o
9300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9301   wire width 8 input 2 \st_pend_i
9302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9303   wire width 8 input 3 \ld_pend_i
9304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9305   wire width 1 $1
9306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9307   wire width 1 $2
9308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9309   cell $reduce_bool $3
9310     parameter \A_SIGNED 1'0
9311     parameter \A_WIDTH 4'1000
9312     parameter \Y_WIDTH 1'1
9313     connect \A \ld_pend_i
9314     connect \Y $2
9315   end
9316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9317   cell $not $4
9318     parameter \A_SIGNED 1'0
9319     parameter \A_WIDTH 1'1
9320     parameter \Y_WIDTH 1'1
9321     connect \A $2
9322     connect \Y $1
9323   end
9324   process $group_0
9325     assign \storable_o 1'0
9326     assign \storable_o $1
9327     sync init
9328   end
9329   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9330   wire width 1 $5
9331   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9332   wire width 1 $6
9333   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9334   cell $reduce_bool $7
9335     parameter \A_SIGNED 1'0
9336     parameter \A_WIDTH 4'1000
9337     parameter \Y_WIDTH 1'1
9338     connect \A \st_pend_i
9339     connect \Y $6
9340   end
9341   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9342   cell $not $8
9343     parameter \A_SIGNED 1'0
9344     parameter \A_WIDTH 1'1
9345     parameter \Y_WIDTH 1'1
9346     connect \A $6
9347     connect \Y $5
9348   end
9349   process $group_1
9350     assign \loadable_o 1'0
9351     assign \loadable_o $5
9352     sync init
9353   end
9354 end
9355 attribute \generator "nMigen"
9356 attribute \nmigen.hierarchy "top.fumemdeps.fur_x3"
9357 module \fur_x3
9358   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9359   wire width 1 output 0 \storable_o
9360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9361   wire width 1 output 1 \loadable_o
9362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9363   wire width 8 input 2 \st_pend_i
9364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9365   wire width 8 input 3 \ld_pend_i
9366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9367   wire width 1 $1
9368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9369   wire width 1 $2
9370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9371   cell $reduce_bool $3
9372     parameter \A_SIGNED 1'0
9373     parameter \A_WIDTH 4'1000
9374     parameter \Y_WIDTH 1'1
9375     connect \A \ld_pend_i
9376     connect \Y $2
9377   end
9378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9379   cell $not $4
9380     parameter \A_SIGNED 1'0
9381     parameter \A_WIDTH 1'1
9382     parameter \Y_WIDTH 1'1
9383     connect \A $2
9384     connect \Y $1
9385   end
9386   process $group_0
9387     assign \storable_o 1'0
9388     assign \storable_o $1
9389     sync init
9390   end
9391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9392   wire width 1 $5
9393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9394   wire width 1 $6
9395   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9396   cell $reduce_bool $7
9397     parameter \A_SIGNED 1'0
9398     parameter \A_WIDTH 4'1000
9399     parameter \Y_WIDTH 1'1
9400     connect \A \st_pend_i
9401     connect \Y $6
9402   end
9403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9404   cell $not $8
9405     parameter \A_SIGNED 1'0
9406     parameter \A_WIDTH 1'1
9407     parameter \Y_WIDTH 1'1
9408     connect \A $6
9409     connect \Y $5
9410   end
9411   process $group_1
9412     assign \loadable_o 1'0
9413     assign \loadable_o $5
9414     sync init
9415   end
9416 end
9417 attribute \generator "nMigen"
9418 attribute \nmigen.hierarchy "top.fumemdeps.fur_x4"
9419 module \fur_x4
9420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9421   wire width 1 output 0 \storable_o
9422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9423   wire width 1 output 1 \loadable_o
9424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9425   wire width 8 input 2 \st_pend_i
9426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9427   wire width 8 input 3 \ld_pend_i
9428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9429   wire width 1 $1
9430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9431   wire width 1 $2
9432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9433   cell $reduce_bool $3
9434     parameter \A_SIGNED 1'0
9435     parameter \A_WIDTH 4'1000
9436     parameter \Y_WIDTH 1'1
9437     connect \A \ld_pend_i
9438     connect \Y $2
9439   end
9440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9441   cell $not $4
9442     parameter \A_SIGNED 1'0
9443     parameter \A_WIDTH 1'1
9444     parameter \Y_WIDTH 1'1
9445     connect \A $2
9446     connect \Y $1
9447   end
9448   process $group_0
9449     assign \storable_o 1'0
9450     assign \storable_o $1
9451     sync init
9452   end
9453   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9454   wire width 1 $5
9455   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9456   wire width 1 $6
9457   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9458   cell $reduce_bool $7
9459     parameter \A_SIGNED 1'0
9460     parameter \A_WIDTH 4'1000
9461     parameter \Y_WIDTH 1'1
9462     connect \A \st_pend_i
9463     connect \Y $6
9464   end
9465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9466   cell $not $8
9467     parameter \A_SIGNED 1'0
9468     parameter \A_WIDTH 1'1
9469     parameter \Y_WIDTH 1'1
9470     connect \A $6
9471     connect \Y $5
9472   end
9473   process $group_1
9474     assign \loadable_o 1'0
9475     assign \loadable_o $5
9476     sync init
9477   end
9478 end
9479 attribute \generator "nMigen"
9480 attribute \nmigen.hierarchy "top.fumemdeps.fur_x5"
9481 module \fur_x5
9482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9483   wire width 1 output 0 \storable_o
9484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9485   wire width 1 output 1 \loadable_o
9486   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9487   wire width 8 input 2 \st_pend_i
9488   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9489   wire width 8 input 3 \ld_pend_i
9490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9491   wire width 1 $1
9492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9493   wire width 1 $2
9494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9495   cell $reduce_bool $3
9496     parameter \A_SIGNED 1'0
9497     parameter \A_WIDTH 4'1000
9498     parameter \Y_WIDTH 1'1
9499     connect \A \ld_pend_i
9500     connect \Y $2
9501   end
9502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9503   cell $not $4
9504     parameter \A_SIGNED 1'0
9505     parameter \A_WIDTH 1'1
9506     parameter \Y_WIDTH 1'1
9507     connect \A $2
9508     connect \Y $1
9509   end
9510   process $group_0
9511     assign \storable_o 1'0
9512     assign \storable_o $1
9513     sync init
9514   end
9515   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9516   wire width 1 $5
9517   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9518   wire width 1 $6
9519   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9520   cell $reduce_bool $7
9521     parameter \A_SIGNED 1'0
9522     parameter \A_WIDTH 4'1000
9523     parameter \Y_WIDTH 1'1
9524     connect \A \st_pend_i
9525     connect \Y $6
9526   end
9527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9528   cell $not $8
9529     parameter \A_SIGNED 1'0
9530     parameter \A_WIDTH 1'1
9531     parameter \Y_WIDTH 1'1
9532     connect \A $6
9533     connect \Y $5
9534   end
9535   process $group_1
9536     assign \loadable_o 1'0
9537     assign \loadable_o $5
9538     sync init
9539   end
9540 end
9541 attribute \generator "nMigen"
9542 attribute \nmigen.hierarchy "top.fumemdeps.fur_x6"
9543 module \fur_x6
9544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9545   wire width 1 output 0 \storable_o
9546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9547   wire width 1 output 1 \loadable_o
9548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9549   wire width 8 input 2 \st_pend_i
9550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9551   wire width 8 input 3 \ld_pend_i
9552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9553   wire width 1 $1
9554   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9555   wire width 1 $2
9556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9557   cell $reduce_bool $3
9558     parameter \A_SIGNED 1'0
9559     parameter \A_WIDTH 4'1000
9560     parameter \Y_WIDTH 1'1
9561     connect \A \ld_pend_i
9562     connect \Y $2
9563   end
9564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9565   cell $not $4
9566     parameter \A_SIGNED 1'0
9567     parameter \A_WIDTH 1'1
9568     parameter \Y_WIDTH 1'1
9569     connect \A $2
9570     connect \Y $1
9571   end
9572   process $group_0
9573     assign \storable_o 1'0
9574     assign \storable_o $1
9575     sync init
9576   end
9577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9578   wire width 1 $5
9579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9580   wire width 1 $6
9581   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9582   cell $reduce_bool $7
9583     parameter \A_SIGNED 1'0
9584     parameter \A_WIDTH 4'1000
9585     parameter \Y_WIDTH 1'1
9586     connect \A \st_pend_i
9587     connect \Y $6
9588   end
9589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9590   cell $not $8
9591     parameter \A_SIGNED 1'0
9592     parameter \A_WIDTH 1'1
9593     parameter \Y_WIDTH 1'1
9594     connect \A $6
9595     connect \Y $5
9596   end
9597   process $group_1
9598     assign \loadable_o 1'0
9599     assign \loadable_o $5
9600     sync init
9601   end
9602 end
9603 attribute \generator "nMigen"
9604 attribute \nmigen.hierarchy "top.fumemdeps.fur_x7"
9605 module \fur_x7
9606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9607   wire width 1 output 0 \storable_o
9608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9609   wire width 1 output 1 \loadable_o
9610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9611   wire width 8 input 2 \st_pend_i
9612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9613   wire width 8 input 3 \ld_pend_i
9614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9615   wire width 1 $1
9616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9617   wire width 1 $2
9618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9619   cell $reduce_bool $3
9620     parameter \A_SIGNED 1'0
9621     parameter \A_WIDTH 4'1000
9622     parameter \Y_WIDTH 1'1
9623     connect \A \ld_pend_i
9624     connect \Y $2
9625   end
9626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9627   cell $not $4
9628     parameter \A_SIGNED 1'0
9629     parameter \A_WIDTH 1'1
9630     parameter \Y_WIDTH 1'1
9631     connect \A $2
9632     connect \Y $1
9633   end
9634   process $group_0
9635     assign \storable_o 1'0
9636     assign \storable_o $1
9637     sync init
9638   end
9639   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9640   wire width 1 $5
9641   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9642   wire width 1 $6
9643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9644   cell $reduce_bool $7
9645     parameter \A_SIGNED 1'0
9646     parameter \A_WIDTH 4'1000
9647     parameter \Y_WIDTH 1'1
9648     connect \A \st_pend_i
9649     connect \Y $6
9650   end
9651   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9652   cell $not $8
9653     parameter \A_SIGNED 1'0
9654     parameter \A_WIDTH 1'1
9655     parameter \Y_WIDTH 1'1
9656     connect \A $6
9657     connect \Y $5
9658   end
9659   process $group_1
9660     assign \loadable_o 1'0
9661     assign \loadable_o $5
9662     sync init
9663   end
9664 end
9665 attribute \generator "nMigen"
9666 attribute \nmigen.hierarchy "top.fumemdeps"
9667 module \fumemdeps
9668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
9669   wire width 8 output 0 \storable_o
9670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
9671   wire width 8 output 1 \loadable_o
9672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
9673   wire width 8 input 2 \ld_pend_i
9674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
9675   wire width 8 input 3 \st_pend_i
9676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
9677   wire width 8 input 4 \go_st_i
9678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
9679   wire width 8 input 5 \go_ld_i
9680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
9681   wire width 8 input 6 \go_die_i
9682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
9683   wire width 8 input 7 \issue_i
9684   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
9685   wire width 1 input 8 \rst
9686   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
9687   wire width 1 input 9 \clk
9688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9689   wire width 8 \dm0_st_wait_o
9690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9691   wire width 8 \dm0_ld_wait_o
9692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9693   wire width 8 \dm0_issue_i
9694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9695   wire width 8 \dm0_go_st_i
9696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9697   wire width 8 \dm0_go_ld_i
9698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9699   wire width 8 \dm0_go_die_i
9700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9701   wire width 8 \dm0_st_pend_i
9702   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9703   wire width 8 \dm0_ld_pend_i
9704   cell \dm0 \dm0
9705     connect \rst \rst
9706     connect \clk \clk
9707     connect \st_wait_o \dm0_st_wait_o
9708     connect \ld_wait_o \dm0_ld_wait_o
9709     connect \issue_i \dm0_issue_i
9710     connect \go_st_i \dm0_go_st_i
9711     connect \go_ld_i \dm0_go_ld_i
9712     connect \go_die_i \dm0_go_die_i
9713     connect \st_pend_i \dm0_st_pend_i
9714     connect \ld_pend_i \dm0_ld_pend_i
9715   end
9716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9717   wire width 8 \dm1_st_wait_o
9718   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9719   wire width 8 \dm1_ld_wait_o
9720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9721   wire width 8 \dm1_issue_i
9722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9723   wire width 8 \dm1_go_st_i
9724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9725   wire width 8 \dm1_go_ld_i
9726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9727   wire width 8 \dm1_go_die_i
9728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9729   wire width 8 \dm1_st_pend_i
9730   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9731   wire width 8 \dm1_ld_pend_i
9732   cell \dm1 \dm1
9733     connect \rst \rst
9734     connect \clk \clk
9735     connect \st_wait_o \dm1_st_wait_o
9736     connect \ld_wait_o \dm1_ld_wait_o
9737     connect \issue_i \dm1_issue_i
9738     connect \go_st_i \dm1_go_st_i
9739     connect \go_ld_i \dm1_go_ld_i
9740     connect \go_die_i \dm1_go_die_i
9741     connect \st_pend_i \dm1_st_pend_i
9742     connect \ld_pend_i \dm1_ld_pend_i
9743   end
9744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9745   wire width 8 \dm2_st_wait_o
9746   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9747   wire width 8 \dm2_ld_wait_o
9748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9749   wire width 8 \dm2_issue_i
9750   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9751   wire width 8 \dm2_go_st_i
9752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9753   wire width 8 \dm2_go_ld_i
9754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9755   wire width 8 \dm2_go_die_i
9756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9757   wire width 8 \dm2_st_pend_i
9758   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9759   wire width 8 \dm2_ld_pend_i
9760   cell \dm2 \dm2
9761     connect \rst \rst
9762     connect \clk \clk
9763     connect \st_wait_o \dm2_st_wait_o
9764     connect \ld_wait_o \dm2_ld_wait_o
9765     connect \issue_i \dm2_issue_i
9766     connect \go_st_i \dm2_go_st_i
9767     connect \go_ld_i \dm2_go_ld_i
9768     connect \go_die_i \dm2_go_die_i
9769     connect \st_pend_i \dm2_st_pend_i
9770     connect \ld_pend_i \dm2_ld_pend_i
9771   end
9772   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9773   wire width 8 \dm3_st_wait_o
9774   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9775   wire width 8 \dm3_ld_wait_o
9776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9777   wire width 8 \dm3_issue_i
9778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9779   wire width 8 \dm3_go_st_i
9780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9781   wire width 8 \dm3_go_ld_i
9782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9783   wire width 8 \dm3_go_die_i
9784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9785   wire width 8 \dm3_st_pend_i
9786   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9787   wire width 8 \dm3_ld_pend_i
9788   cell \dm3 \dm3
9789     connect \rst \rst
9790     connect \clk \clk
9791     connect \st_wait_o \dm3_st_wait_o
9792     connect \ld_wait_o \dm3_ld_wait_o
9793     connect \issue_i \dm3_issue_i
9794     connect \go_st_i \dm3_go_st_i
9795     connect \go_ld_i \dm3_go_ld_i
9796     connect \go_die_i \dm3_go_die_i
9797     connect \st_pend_i \dm3_st_pend_i
9798     connect \ld_pend_i \dm3_ld_pend_i
9799   end
9800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9801   wire width 8 \dm4_st_wait_o
9802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9803   wire width 8 \dm4_ld_wait_o
9804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9805   wire width 8 \dm4_issue_i
9806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9807   wire width 8 \dm4_go_st_i
9808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9809   wire width 8 \dm4_go_ld_i
9810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9811   wire width 8 \dm4_go_die_i
9812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9813   wire width 8 \dm4_st_pend_i
9814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9815   wire width 8 \dm4_ld_pend_i
9816   cell \dm4 \dm4
9817     connect \rst \rst
9818     connect \clk \clk
9819     connect \st_wait_o \dm4_st_wait_o
9820     connect \ld_wait_o \dm4_ld_wait_o
9821     connect \issue_i \dm4_issue_i
9822     connect \go_st_i \dm4_go_st_i
9823     connect \go_ld_i \dm4_go_ld_i
9824     connect \go_die_i \dm4_go_die_i
9825     connect \st_pend_i \dm4_st_pend_i
9826     connect \ld_pend_i \dm4_ld_pend_i
9827   end
9828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9829   wire width 8 \dm5_st_wait_o
9830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9831   wire width 8 \dm5_ld_wait_o
9832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9833   wire width 8 \dm5_issue_i
9834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9835   wire width 8 \dm5_go_st_i
9836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9837   wire width 8 \dm5_go_ld_i
9838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9839   wire width 8 \dm5_go_die_i
9840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9841   wire width 8 \dm5_st_pend_i
9842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9843   wire width 8 \dm5_ld_pend_i
9844   cell \dm5 \dm5
9845     connect \rst \rst
9846     connect \clk \clk
9847     connect \st_wait_o \dm5_st_wait_o
9848     connect \ld_wait_o \dm5_ld_wait_o
9849     connect \issue_i \dm5_issue_i
9850     connect \go_st_i \dm5_go_st_i
9851     connect \go_ld_i \dm5_go_ld_i
9852     connect \go_die_i \dm5_go_die_i
9853     connect \st_pend_i \dm5_st_pend_i
9854     connect \ld_pend_i \dm5_ld_pend_i
9855   end
9856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9857   wire width 8 \dm6_st_wait_o
9858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9859   wire width 8 \dm6_ld_wait_o
9860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9861   wire width 8 \dm6_issue_i
9862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9863   wire width 8 \dm6_go_st_i
9864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9865   wire width 8 \dm6_go_ld_i
9866   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9867   wire width 8 \dm6_go_die_i
9868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9869   wire width 8 \dm6_st_pend_i
9870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9871   wire width 8 \dm6_ld_pend_i
9872   cell \dm6 \dm6
9873     connect \rst \rst
9874     connect \clk \clk
9875     connect \st_wait_o \dm6_st_wait_o
9876     connect \ld_wait_o \dm6_ld_wait_o
9877     connect \issue_i \dm6_issue_i
9878     connect \go_st_i \dm6_go_st_i
9879     connect \go_ld_i \dm6_go_ld_i
9880     connect \go_die_i \dm6_go_die_i
9881     connect \st_pend_i \dm6_st_pend_i
9882     connect \ld_pend_i \dm6_ld_pend_i
9883   end
9884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9885   wire width 8 \dm7_st_wait_o
9886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9887   wire width 8 \dm7_ld_wait_o
9888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9889   wire width 8 \dm7_issue_i
9890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9891   wire width 8 \dm7_go_st_i
9892   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9893   wire width 8 \dm7_go_ld_i
9894   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9895   wire width 8 \dm7_go_die_i
9896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9897   wire width 8 \dm7_st_pend_i
9898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9899   wire width 8 \dm7_ld_pend_i
9900   cell \dm7 \dm7
9901     connect \rst \rst
9902     connect \clk \clk
9903     connect \st_wait_o \dm7_st_wait_o
9904     connect \ld_wait_o \dm7_ld_wait_o
9905     connect \issue_i \dm7_issue_i
9906     connect \go_st_i \dm7_go_st_i
9907     connect \go_ld_i \dm7_go_ld_i
9908     connect \go_die_i \dm7_go_die_i
9909     connect \st_pend_i \dm7_st_pend_i
9910     connect \ld_pend_i \dm7_ld_pend_i
9911   end
9912   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9913   wire width 1 \fur_x0_storable_o
9914   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9915   wire width 1 \fur_x0_loadable_o
9916   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9917   wire width 8 \fur_x0_st_pend_i
9918   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9919   wire width 8 \fur_x0_ld_pend_i
9920   cell \fur_x0 \fur_x0
9921     connect \storable_o \fur_x0_storable_o
9922     connect \loadable_o \fur_x0_loadable_o
9923     connect \st_pend_i \fur_x0_st_pend_i
9924     connect \ld_pend_i \fur_x0_ld_pend_i
9925   end
9926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9927   wire width 1 \fur_x1_storable_o
9928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9929   wire width 1 \fur_x1_loadable_o
9930   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9931   wire width 8 \fur_x1_st_pend_i
9932   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9933   wire width 8 \fur_x1_ld_pend_i
9934   cell \fur_x1 \fur_x1
9935     connect \storable_o \fur_x1_storable_o
9936     connect \loadable_o \fur_x1_loadable_o
9937     connect \st_pend_i \fur_x1_st_pend_i
9938     connect \ld_pend_i \fur_x1_ld_pend_i
9939   end
9940   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9941   wire width 1 \fur_x2_storable_o
9942   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9943   wire width 1 \fur_x2_loadable_o
9944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9945   wire width 8 \fur_x2_st_pend_i
9946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9947   wire width 8 \fur_x2_ld_pend_i
9948   cell \fur_x2 \fur_x2
9949     connect \storable_o \fur_x2_storable_o
9950     connect \loadable_o \fur_x2_loadable_o
9951     connect \st_pend_i \fur_x2_st_pend_i
9952     connect \ld_pend_i \fur_x2_ld_pend_i
9953   end
9954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9955   wire width 1 \fur_x3_storable_o
9956   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9957   wire width 1 \fur_x3_loadable_o
9958   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9959   wire width 8 \fur_x3_st_pend_i
9960   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9961   wire width 8 \fur_x3_ld_pend_i
9962   cell \fur_x3 \fur_x3
9963     connect \storable_o \fur_x3_storable_o
9964     connect \loadable_o \fur_x3_loadable_o
9965     connect \st_pend_i \fur_x3_st_pend_i
9966     connect \ld_pend_i \fur_x3_ld_pend_i
9967   end
9968   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9969   wire width 1 \fur_x4_storable_o
9970   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9971   wire width 1 \fur_x4_loadable_o
9972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9973   wire width 8 \fur_x4_st_pend_i
9974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9975   wire width 8 \fur_x4_ld_pend_i
9976   cell \fur_x4 \fur_x4
9977     connect \storable_o \fur_x4_storable_o
9978     connect \loadable_o \fur_x4_loadable_o
9979     connect \st_pend_i \fur_x4_st_pend_i
9980     connect \ld_pend_i \fur_x4_ld_pend_i
9981   end
9982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9983   wire width 1 \fur_x5_storable_o
9984   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9985   wire width 1 \fur_x5_loadable_o
9986   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9987   wire width 8 \fur_x5_st_pend_i
9988   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9989   wire width 8 \fur_x5_ld_pend_i
9990   cell \fur_x5 \fur_x5
9991     connect \storable_o \fur_x5_storable_o
9992     connect \loadable_o \fur_x5_loadable_o
9993     connect \st_pend_i \fur_x5_st_pend_i
9994     connect \ld_pend_i \fur_x5_ld_pend_i
9995   end
9996   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9997   wire width 1 \fur_x6_storable_o
9998   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9999   wire width 1 \fur_x6_loadable_o
10000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
10001   wire width 8 \fur_x6_st_pend_i
10002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
10003   wire width 8 \fur_x6_ld_pend_i
10004   cell \fur_x6 \fur_x6
10005     connect \storable_o \fur_x6_storable_o
10006     connect \loadable_o \fur_x6_loadable_o
10007     connect \st_pend_i \fur_x6_st_pend_i
10008     connect \ld_pend_i \fur_x6_ld_pend_i
10009   end
10010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
10011   wire width 1 \fur_x7_storable_o
10012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
10013   wire width 1 \fur_x7_loadable_o
10014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
10015   wire width 8 \fur_x7_st_pend_i
10016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
10017   wire width 8 \fur_x7_ld_pend_i
10018   cell \fur_x7 \fur_x7
10019     connect \storable_o \fur_x7_storable_o
10020     connect \loadable_o \fur_x7_loadable_o
10021     connect \st_pend_i \fur_x7_st_pend_i
10022     connect \ld_pend_i \fur_x7_ld_pend_i
10023   end
10024   process $group_0
10025     assign \storable_o 8'00000000
10026     assign \storable_o { \fur_x7_storable_o \fur_x6_storable_o \fur_x5_storable_o \fur_x4_storable_o \fur_x3_storable_o \fur_x2_storable_o \fur_x1_storable_o \fur_x0_storable_o }
10027     sync init
10028   end
10029   process $group_1
10030     assign \loadable_o 8'00000000
10031     assign \loadable_o { \fur_x7_loadable_o \fur_x6_loadable_o \fur_x5_loadable_o \fur_x4_loadable_o \fur_x3_loadable_o \fur_x2_loadable_o \fur_x1_loadable_o \fur_x0_loadable_o }
10032     sync init
10033   end
10034   process $group_2
10035     assign \fur_x0_st_pend_i 8'00000000
10036     assign \fur_x0_st_pend_i \dm0_st_wait_o
10037     sync init
10038   end
10039   process $group_3
10040     assign \fur_x0_ld_pend_i 8'00000000
10041     assign \fur_x0_ld_pend_i \dm0_ld_wait_o
10042     sync init
10043   end
10044   process $group_4
10045     assign \fur_x1_st_pend_i 8'00000000
10046     assign \fur_x1_st_pend_i \dm1_st_wait_o
10047     sync init
10048   end
10049   process $group_5
10050     assign \fur_x1_ld_pend_i 8'00000000
10051     assign \fur_x1_ld_pend_i \dm1_ld_wait_o
10052     sync init
10053   end
10054   process $group_6
10055     assign \fur_x2_st_pend_i 8'00000000
10056     assign \fur_x2_st_pend_i \dm2_st_wait_o
10057     sync init
10058   end
10059   process $group_7
10060     assign \fur_x2_ld_pend_i 8'00000000
10061     assign \fur_x2_ld_pend_i \dm2_ld_wait_o
10062     sync init
10063   end
10064   process $group_8
10065     assign \fur_x3_st_pend_i 8'00000000
10066     assign \fur_x3_st_pend_i \dm3_st_wait_o
10067     sync init
10068   end
10069   process $group_9
10070     assign \fur_x3_ld_pend_i 8'00000000
10071     assign \fur_x3_ld_pend_i \dm3_ld_wait_o
10072     sync init
10073   end
10074   process $group_10
10075     assign \fur_x4_st_pend_i 8'00000000
10076     assign \fur_x4_st_pend_i \dm4_st_wait_o
10077     sync init
10078   end
10079   process $group_11
10080     assign \fur_x4_ld_pend_i 8'00000000
10081     assign \fur_x4_ld_pend_i \dm4_ld_wait_o
10082     sync init
10083   end
10084   process $group_12
10085     assign \fur_x5_st_pend_i 8'00000000
10086     assign \fur_x5_st_pend_i \dm5_st_wait_o
10087     sync init
10088   end
10089   process $group_13
10090     assign \fur_x5_ld_pend_i 8'00000000
10091     assign \fur_x5_ld_pend_i \dm5_ld_wait_o
10092     sync init
10093   end
10094   process $group_14
10095     assign \fur_x6_st_pend_i 8'00000000
10096     assign \fur_x6_st_pend_i \dm6_st_wait_o
10097     sync init
10098   end
10099   process $group_15
10100     assign \fur_x6_ld_pend_i 8'00000000
10101     assign \fur_x6_ld_pend_i \dm6_ld_wait_o
10102     sync init
10103   end
10104   process $group_16
10105     assign \fur_x7_st_pend_i 8'00000000
10106     assign \fur_x7_st_pend_i \dm7_st_wait_o
10107     sync init
10108   end
10109   process $group_17
10110     assign \fur_x7_ld_pend_i 8'00000000
10111     assign \fur_x7_ld_pend_i \dm7_ld_wait_o
10112     sync init
10113   end
10114   process $group_18
10115     assign \dm0_issue_i 8'00000000
10116     assign \dm1_issue_i 8'00000000
10117     assign \dm2_issue_i 8'00000000
10118     assign \dm3_issue_i 8'00000000
10119     assign \dm4_issue_i 8'00000000
10120     assign \dm5_issue_i 8'00000000
10121     assign \dm6_issue_i 8'00000000
10122     assign \dm7_issue_i 8'00000000
10123     assign { \dm7_issue_i [0] \dm6_issue_i [0] \dm5_issue_i [0] \dm4_issue_i [0] \dm3_issue_i [0] \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i
10124     assign { \dm7_issue_i [1] \dm6_issue_i [1] \dm5_issue_i [1] \dm4_issue_i [1] \dm3_issue_i [1] \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i
10125     assign { \dm7_issue_i [2] \dm6_issue_i [2] \dm5_issue_i [2] \dm4_issue_i [2] \dm3_issue_i [2] \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i
10126     assign { \dm7_issue_i [3] \dm6_issue_i [3] \dm5_issue_i [3] \dm4_issue_i [3] \dm3_issue_i [3] \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i
10127     assign { \dm7_issue_i [4] \dm6_issue_i [4] \dm5_issue_i [4] \dm4_issue_i [4] \dm3_issue_i [4] \dm2_issue_i [4] \dm1_issue_i [4] \dm0_issue_i [4] } \issue_i
10128     assign { \dm7_issue_i [5] \dm6_issue_i [5] \dm5_issue_i [5] \dm4_issue_i [5] \dm3_issue_i [5] \dm2_issue_i [5] \dm1_issue_i [5] \dm0_issue_i [5] } \issue_i
10129     assign { \dm7_issue_i [6] \dm6_issue_i [6] \dm5_issue_i [6] \dm4_issue_i [6] \dm3_issue_i [6] \dm2_issue_i [6] \dm1_issue_i [6] \dm0_issue_i [6] } \issue_i
10130     assign { \dm7_issue_i [7] \dm6_issue_i [7] \dm5_issue_i [7] \dm4_issue_i [7] \dm3_issue_i [7] \dm2_issue_i [7] \dm1_issue_i [7] \dm0_issue_i [7] } \issue_i
10131     sync init
10132   end
10133   process $group_26
10134     assign \dm0_go_st_i 8'00000000
10135     assign \dm0_go_st_i \go_st_i
10136     sync init
10137   end
10138   process $group_27
10139     assign \dm0_go_ld_i 8'00000000
10140     assign \dm0_go_ld_i \go_ld_i
10141     sync init
10142   end
10143   process $group_28
10144     assign \dm0_go_die_i 8'00000000
10145     assign \dm0_go_die_i \go_die_i
10146     sync init
10147   end
10148   process $group_29
10149     assign \dm1_go_st_i 8'00000000
10150     assign \dm1_go_st_i \go_st_i
10151     sync init
10152   end
10153   process $group_30
10154     assign \dm1_go_ld_i 8'00000000
10155     assign \dm1_go_ld_i \go_ld_i
10156     sync init
10157   end
10158   process $group_31
10159     assign \dm1_go_die_i 8'00000000
10160     assign \dm1_go_die_i \go_die_i
10161     sync init
10162   end
10163   process $group_32
10164     assign \dm2_go_st_i 8'00000000
10165     assign \dm2_go_st_i \go_st_i
10166     sync init
10167   end
10168   process $group_33
10169     assign \dm2_go_ld_i 8'00000000
10170     assign \dm2_go_ld_i \go_ld_i
10171     sync init
10172   end
10173   process $group_34
10174     assign \dm2_go_die_i 8'00000000
10175     assign \dm2_go_die_i \go_die_i
10176     sync init
10177   end
10178   process $group_35
10179     assign \dm3_go_st_i 8'00000000
10180     assign \dm3_go_st_i \go_st_i
10181     sync init
10182   end
10183   process $group_36
10184     assign \dm3_go_ld_i 8'00000000
10185     assign \dm3_go_ld_i \go_ld_i
10186     sync init
10187   end
10188   process $group_37
10189     assign \dm3_go_die_i 8'00000000
10190     assign \dm3_go_die_i \go_die_i
10191     sync init
10192   end
10193   process $group_38
10194     assign \dm4_go_st_i 8'00000000
10195     assign \dm4_go_st_i \go_st_i
10196     sync init
10197   end
10198   process $group_39
10199     assign \dm4_go_ld_i 8'00000000
10200     assign \dm4_go_ld_i \go_ld_i
10201     sync init
10202   end
10203   process $group_40
10204     assign \dm4_go_die_i 8'00000000
10205     assign \dm4_go_die_i \go_die_i
10206     sync init
10207   end
10208   process $group_41
10209     assign \dm5_go_st_i 8'00000000
10210     assign \dm5_go_st_i \go_st_i
10211     sync init
10212   end
10213   process $group_42
10214     assign \dm5_go_ld_i 8'00000000
10215     assign \dm5_go_ld_i \go_ld_i
10216     sync init
10217   end
10218   process $group_43
10219     assign \dm5_go_die_i 8'00000000
10220     assign \dm5_go_die_i \go_die_i
10221     sync init
10222   end
10223   process $group_44
10224     assign \dm6_go_st_i 8'00000000
10225     assign \dm6_go_st_i \go_st_i
10226     sync init
10227   end
10228   process $group_45
10229     assign \dm6_go_ld_i 8'00000000
10230     assign \dm6_go_ld_i \go_ld_i
10231     sync init
10232   end
10233   process $group_46
10234     assign \dm6_go_die_i 8'00000000
10235     assign \dm6_go_die_i \go_die_i
10236     sync init
10237   end
10238   process $group_47
10239     assign \dm7_go_st_i 8'00000000
10240     assign \dm7_go_st_i \go_st_i
10241     sync init
10242   end
10243   process $group_48
10244     assign \dm7_go_ld_i 8'00000000
10245     assign \dm7_go_ld_i \go_ld_i
10246     sync init
10247   end
10248   process $group_49
10249     assign \dm7_go_die_i 8'00000000
10250     assign \dm7_go_die_i \go_die_i
10251     sync init
10252   end
10253   process $group_50
10254     assign \dm0_st_pend_i 8'00000000
10255     assign \dm0_st_pend_i \st_pend_i
10256     sync init
10257   end
10258   process $group_51
10259     assign \dm0_ld_pend_i 8'00000000
10260     assign \dm0_ld_pend_i \ld_pend_i
10261     sync init
10262   end
10263   process $group_52
10264     assign \dm1_st_pend_i 8'00000000
10265     assign \dm1_st_pend_i \st_pend_i
10266     sync init
10267   end
10268   process $group_53
10269     assign \dm1_ld_pend_i 8'00000000
10270     assign \dm1_ld_pend_i \ld_pend_i
10271     sync init
10272   end
10273   process $group_54
10274     assign \dm2_st_pend_i 8'00000000
10275     assign \dm2_st_pend_i \st_pend_i
10276     sync init
10277   end
10278   process $group_55
10279     assign \dm2_ld_pend_i 8'00000000
10280     assign \dm2_ld_pend_i \ld_pend_i
10281     sync init
10282   end
10283   process $group_56
10284     assign \dm3_st_pend_i 8'00000000
10285     assign \dm3_st_pend_i \st_pend_i
10286     sync init
10287   end
10288   process $group_57
10289     assign \dm3_ld_pend_i 8'00000000
10290     assign \dm3_ld_pend_i \ld_pend_i
10291     sync init
10292   end
10293   process $group_58
10294     assign \dm4_st_pend_i 8'00000000
10295     assign \dm4_st_pend_i \st_pend_i
10296     sync init
10297   end
10298   process $group_59
10299     assign \dm4_ld_pend_i 8'00000000
10300     assign \dm4_ld_pend_i \ld_pend_i
10301     sync init
10302   end
10303   process $group_60
10304     assign \dm5_st_pend_i 8'00000000
10305     assign \dm5_st_pend_i \st_pend_i
10306     sync init
10307   end
10308   process $group_61
10309     assign \dm5_ld_pend_i 8'00000000
10310     assign \dm5_ld_pend_i \ld_pend_i
10311     sync init
10312   end
10313   process $group_62
10314     assign \dm6_st_pend_i 8'00000000
10315     assign \dm6_st_pend_i \st_pend_i
10316     sync init
10317   end
10318   process $group_63
10319     assign \dm6_ld_pend_i 8'00000000
10320     assign \dm6_ld_pend_i \ld_pend_i
10321     sync init
10322   end
10323   process $group_64
10324     assign \dm7_st_pend_i 8'00000000
10325     assign \dm7_st_pend_i \st_pend_i
10326     sync init
10327   end
10328   process $group_65
10329     assign \dm7_ld_pend_i 8'00000000
10330     assign \dm7_ld_pend_i \ld_pend_i
10331     sync init
10332   end
10333 end
10334 attribute \generator "nMigen"
10335 attribute \top 1
10336 attribute \nmigen.hierarchy "test_mem_fus"
10337 module \test_mem_fus
10338   attribute \src "scoreboard/test_mem_fu_matrix.py:72"
10339   wire width 8 input 0 \ld_i
10340   attribute \src "scoreboard/test_mem_fu_matrix.py:73"
10341   wire width 8 input 1 \st_i
10342   attribute \src "scoreboard/test_mem_fu_matrix.py:84"
10343   wire width 8 input 2 \req_rel_i
10344   attribute \src "scoreboard/test_mem_fu_matrix.py:85"
10345   wire width 8 output 3 \loadable_o
10346   attribute \src "scoreboard/test_mem_fu_matrix.py:86"
10347   wire width 8 output 4 \storable_o
10348   attribute \src "scoreboard/test_mem_fu_matrix.py:75"
10349   wire width 8 input 5 \load_hit_i
10350   attribute \src "scoreboard/test_mem_fu_matrix.py:76"
10351   wire width 8 input 6 \stwd_hit_i
10352   attribute \src "scoreboard/test_mem_fu_matrix.py:88"
10353   wire width 8 input 7 \go_st_i
10354   attribute \src "scoreboard/test_mem_fu_matrix.py:89"
10355   wire width 8 input 8 \go_ld_i
10356   attribute \src "scoreboard/test_mem_fu_matrix.py:90"
10357   wire width 8 input 9 \go_die_i
10358   attribute \src "scoreboard/test_mem_fu_matrix.py:91"
10359   wire width 8 input 10 \req_rel_o
10360   attribute \src "scoreboard/test_mem_fu_matrix.py:92"
10361   wire width 8 input 11 \fn_issue_i
10362   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
10363   wire width 1 input 12 \clk
10364   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
10365   wire width 1 input 13 \rst
10366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
10367   wire width 8 \ldstdeps_ld_pend_i
10368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
10369   wire width 8 \ldstdeps_st_pend_i
10370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
10371   wire width 8 \ldstdeps_issue_i
10372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
10373   wire width 8 \ldstdeps_load_hit_i
10374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
10375   wire width 8 \ldstdeps_stwd_hit_i
10376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
10377   wire width 8 \ldstdeps_go_die_i
10378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
10379   wire width 8 \ldstdeps_ld_hold_st_o
10380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
10381   wire width 8 \ldstdeps_st_hold_ld_o
10382   cell \ldstdeps \ldstdeps
10383     connect \ld_pend_i \ldstdeps_ld_pend_i
10384     connect \st_pend_i \ldstdeps_st_pend_i
10385     connect \issue_i \ldstdeps_issue_i
10386     connect \load_hit_i \ldstdeps_load_hit_i
10387     connect \stwd_hit_i \ldstdeps_stwd_hit_i
10388     connect \go_die_i \ldstdeps_go_die_i
10389     connect \ld_hold_st_o \ldstdeps_ld_hold_st_o
10390     connect \st_hold_ld_o \ldstdeps_st_hold_ld_o
10391     connect \rst \rst
10392     connect \clk \clk
10393   end
10394   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
10395   wire width 8 \fumemdeps_storable_o
10396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
10397   wire width 8 \fumemdeps_loadable_o
10398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
10399   wire width 8 \fumemdeps_ld_pend_i
10400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
10401   wire width 8 \fumemdeps_st_pend_i
10402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
10403   wire width 8 \fumemdeps_go_st_i
10404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
10405   wire width 8 \fumemdeps_go_ld_i
10406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
10407   wire width 8 \fumemdeps_go_die_i
10408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
10409   wire width 8 \fumemdeps_issue_i
10410   cell \fumemdeps \fumemdeps
10411     connect \storable_o \fumemdeps_storable_o
10412     connect \loadable_o \fumemdeps_loadable_o
10413     connect \ld_pend_i \fumemdeps_ld_pend_i
10414     connect \st_pend_i \fumemdeps_st_pend_i
10415     connect \go_st_i \fumemdeps_go_st_i
10416     connect \go_ld_i \fumemdeps_go_ld_i
10417     connect \go_die_i \fumemdeps_go_die_i
10418     connect \issue_i \fumemdeps_issue_i
10419     connect \rst \rst
10420     connect \clk \clk
10421   end
10422   process $group_0
10423     assign \ldstdeps_ld_pend_i 8'00000000
10424     assign \ldstdeps_ld_pend_i \ld_i
10425     sync init
10426   end
10427   process $group_1
10428     assign \ldstdeps_st_pend_i 8'00000000
10429     assign \ldstdeps_st_pend_i \st_i
10430     sync init
10431   end
10432   process $group_2
10433     assign \ldstdeps_issue_i 8'00000000
10434     assign \ldstdeps_issue_i \fn_issue_i
10435     sync init
10436   end
10437   process $group_3
10438     assign \ldstdeps_load_hit_i 8'00000000
10439     assign \ldstdeps_load_hit_i \load_hit_i
10440     sync init
10441   end
10442   process $group_4
10443     assign \ldstdeps_stwd_hit_i 8'00000000
10444     assign \ldstdeps_stwd_hit_i \stwd_hit_i
10445     sync init
10446   end
10447   process $group_5
10448     assign \ldstdeps_go_die_i 8'00000000
10449     assign \ldstdeps_go_die_i \go_die_i
10450     sync init
10451   end
10452   process $group_6
10453     assign \storable_o 8'00000000
10454     assign \storable_o \fumemdeps_storable_o
10455     sync init
10456   end
10457   process $group_7
10458     assign \loadable_o 8'00000000
10459     assign \loadable_o \fumemdeps_loadable_o
10460     sync init
10461   end
10462   process $group_8
10463     assign \fumemdeps_ld_pend_i 8'00000000
10464     assign \fumemdeps_ld_pend_i \ldstdeps_ld_hold_st_o
10465     sync init
10466   end
10467   process $group_9
10468     assign \fumemdeps_st_pend_i 8'00000000
10469     assign \fumemdeps_st_pend_i \ldstdeps_st_hold_ld_o
10470     sync init
10471   end
10472   process $group_10
10473     assign \fumemdeps_go_st_i 8'00000000
10474     assign \fumemdeps_go_st_i \stwd_hit_i
10475     sync init
10476   end
10477   process $group_11
10478     assign \fumemdeps_go_ld_i 8'00000000
10479     assign \fumemdeps_go_ld_i \load_hit_i
10480     sync init
10481   end
10482   process $group_12
10483     assign \fumemdeps_go_die_i 8'00000000
10484     assign \fumemdeps_go_die_i \go_die_i
10485     sync init
10486   end
10487   process $group_13
10488     assign \fumemdeps_issue_i 8'00000000
10489     assign \fumemdeps_issue_i \fn_issue_i
10490     sync init
10491   end
10492 end