rename ls180sram4k to ls180
[soclayout.git] / experiments9 / GUIDELINES.rst
1
2
3 ================================
4 Quick Guidelines on Floorplaning
5 ================================
6
7
8 Some hints about how to avoid common pitfall making the floorplan.
9
10 Terminology:
11
12 * ``Cell`` : Even if in Hurricane it contain both the netlist and
13 the layout, in this context we will consider it as a pure netlist.
14
15 * ``Block`` : The Python class wrapper around a ``Cell`` to change it
16 into a placed and routed layout used as black box by the above
17 hierarchical levels. It is both the program that perform the P&R
18 and a cache for upper levels.
19 If it contains no sub-blocks, it is placed flat (virtual flatten).
20
21
22 Disclaimer
23 ==========
24
25 At this moment, the Block tools can hardly be called floorplaner.
26 They provides very basic facility for manual floorplanning.
27
28
29 Layout Caching
30 ==============
31
32 To create a block from a ``Cell``:
33
34 .. code-block:: python
35
36 add = af.getCell( 'add', CRL.Catalog.State.Views )
37 blockAdd = Block.create \
38 ( add
39 , ioPins=[ (IoPin.SOUTH|IoPin.A_BEGIN, 'a({})', l( 10.0), l(20.0), 16)
40 , (IoPin.SOUTH|IoPin.A_BEGIN, 'b({})', l( 20.0), l(20.0), 16)
41 , (IoPin.NORTH|IoPin.A_BEGIN, 'o({})', l(100.0), l(10.0), 16)
42 ]
43 )
44 blockAdd.state.cfg.etesian.spaceMargin = 0.10
45 blockAdd.state.fixedHeight = l(400)
46 blockAdd.state.useSpares = False
47 blockAdd.state.editor = editor
48 rvalue = blockAdd.build()
49
50
51 If you load the ``Cell`` with the flag ``CRL.Catalog.State.Views``, the
52 parser will attemps to load both the netlist (mandatory) and the layout.
53 If the layout is present, then the block **will not be P&R again**,
54 the current layout is reused.
55
56 If you want to selectivelely rebuild one block, you can either remove
57 the relevant ``ap`` file or change the loading flag to:
58
59 .. code-block:: python
60
61 add = af.getCell( 'add', CRL.Catalog.State.Logical )
62
63
64 Pin Placement
65 =============
66
67 Pin placement is critical both for the P&R of the block and the one
68 of the above level. So here is some hints.
69
70 * Do not pack pin as closely as possible. Try to leave at least one
71 free pitch between them. Otherwise it may create huge contention
72 point both inside the block and outside to access the block.
73
74 * If there is a *sliced* structure, that is one same treatment is
75 done for each bit of the I/O busses, interleave the relevant
76 busses pins. For examle, instead of having: ::
77
78 a(0) a(1) a(2) a(3) b(0) b(1) b(2) b(3)
79
80 Try: ::
81
82 a(0) b(0) a(1) b(1) a(2) b(2) a(3) b(3)
83
84
85 Aspect Ratio (aka Form Factor)
86 ==============================
87
88 It is important to consider that the routing capacity in one direction
89 is directly proportional to the length of the side of the abutment box
90 in the perpandicular direction. So, if you make a very *flat* box,
91 the number of horizontal tracks became limited, and may become not
92 routable.
93
94 This effect is related to the kind of graph of the netlist. If it
95 has a strong pipeline structure, a very elongated shape may be still
96 be possible.
97
98
99 The Halo Parameter
100 ==================
101
102 By default, the global router will search to connect all pins of a Net
103 in the square area defined by the pins, inflated by the halo (the halo
104 is given in number of GCells, that is the height of a standard cell).
105 A problem arise if you have a net of only two pins (usually 60% of the
106 nets are like that), each across of a huge block. To avoid being stuck,
107 the halo must be increased by at least half the size of the biggest
108 block dimension. Note that, by drastically increasing the search area
109 it may slow down much the global router.
110
111 .. code-block:: python
112
113 blockIssuer.state.cfg.katana.searchHalo = 10000
114