experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5              YOSYS_FLATTEN = No
   6 #            YOSYS_SET_TOP = Yes
   7                     CHIP  = chip
   8                     CORE  = ls180
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                  USE_KITE = No
  12                  RM_CHIP  = Yes
  13                  # must make VST names unique (for re-importing to GHDL)
  14                 VST_FLAGS = --vst-uniquify-uppercase
  15
  16                  #NETLISTS = $(shell cat cells.lst)
  17                  NETLISTS = ls180 libresoc
  18 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  19
  20
  21
  22  include ./mk/design-flow.mk
  23
  24 chip_r.vst: ls180.vst
  25         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  26
  27 chip_r.ap: chip_r.vst
  28
  29 pinmux:
  30         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  31         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  32         ln -f -s coriolis2/ls180 ls180
  33
  34 # comment out for now
  35 blif:      ls180.blif
  36 vst:       ls180.vst
  37
  38 lvx:       lvx-chip_r
  39 druc:      druc-chip_r
  40 dreal:     dreal-chip_r
  41 flatph:     flatph-chip_r
  42 view:      cgt-chip_r
  43
  44 layout:    chip_r.ap
  45 gds:       chip_r.gds
  46 gds_flat:  chip_r_flat.gds
  47 cif:       chip_r.cif
  48
  49
  50 view:      cgt-chip_r
  51 sim:       asimut-ls180_r