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include (but do not use) FreePDK45 in experiments10
[soclayout.git] / experiments10 /
2021-04-12 Luke Kenneth Casso... rename JTAG port in adder test experiments10_verilog... tree | commitdiff
2021-04-01 Luke Kenneth Casso... run doChipFloorplan in experiments10 tree | commitdiff
2021-04-01 Luke Kenneth Casso... increase experiment10 JTAG tap width to 4 tree | commitdiff
2020-11-12 Luke Kenneth Casso... remove io_in/io_out from niolib experiments10 tree | commitdiff
2020-11-04 Luke Kenneth Casso... minor reformat of spec, whitespace tree | commitdiff
2020-11-02 Jean-Paul ChaputCompleted experiment10, adder with JTAG (dual clocks... tree | commitdiff
2020-10-25 Jean-Paul ChaputAdded one-clock generated add.vst. tree | commitdiff
2020-10-25 Jean-Paul ChaputExperiment10 switched to the new chip2core module. tree | commitdiff
2020-10-25 Luke Kenneth Casso... update non_generated add.il for convenience tree | commitdiff
2020-10-24 Luke Kenneth Casso... add feedback shift register back in tree | commitdiff
2020-10-22 Luke Kenneth Casso... add non-generated add.il tree | commitdiff
2020-10-22 Luke Kenneth Casso... add jtag IO to experiment10 tree | commitdiff
2020-10-22 Luke Kenneth Casso... add JTAG test tree | commitdiff
2020-10-22 Luke Kenneth Casso... add experiments10, to add C4M JTAG tree | commitdiff