increase chip size by 100, make chipSize closer to ring
[soclayout.git] / experiments9 / coriolis2 /
2020-11-08 Luke Kenneth Casso... start conversion of ls180 to new niolib
2020-11-05 Luke Kenneth Casso... update to "full" core
2020-10-04 Luke Kenneth Casso... match up power/gnd numbers with pinmux
2020-10-04 Luke Kenneth Casso... use new extpower/intpower and pads.useCoreSize params
2020-10-02 Luke Kenneth Casso... really really cut down core
2020-10-02 Luke Kenneth Casso... move ioring to pinmux
2020-10-01 Luke Kenneth Casso... sort sys_* pad names
2020-10-01 Luke Kenneth Casso... add I2C, allow sys_clk_i and sys_pll_48_o out
2020-09-30 Luke Kenneth Casso... increase core.size to 27500x27500
2020-09-30 Luke Kenneth Casso... commented-out core.size and chip.size which would allow the
2020-09-29 Luke Kenneth Casso... add cki and ck to clock settings
2020-09-28 Luke Kenneth Casso... add sdram_dm_1 back in
2020-09-28 Luke Kenneth Casso... iopad pads.instances mapping
2020-09-28 Luke Kenneth Casso... cut definition of clocks back to minimum
2020-09-28 Luke Kenneth Casso... connect up dummy "NC" pins
2020-09-27 Luke Kenneth Casso... add soc ioring
2020-08-13 Luke Kenneth Casso... whitespace cleanup
2020-08-13 Luke Kenneth Casso... whoops must use "with" on CfgCache
2020-08-12 Jean-Paul ChaputAdded doDesignFlat.py to P&R issuer in a flat way.
2020-08-11 Jean-Paul ChaputCorrect taking in accounts of the parameters settings.
2020-08-11 Luke Kenneth Casso... fix coriolis2 settings to use new CfgCache
2020-08-07 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2020-08-07 Jean-Paul ChaputUse of CfgCache. Little beautificaton of doDesign.py
2020-08-03 Jean-Paul ChaputFisrt attempt at floorplaning test_issuer.
2020-06-30 Jean-Paul ChaputAdded experments9, a first taste at the full scale...