src/soc/clock/dummypll.py

   1 """a Dummy PLL module to be replaced by a real one
   2 """
   3
   4 from nmigen import (Module, Signal, Elaboratable, Const, Cat, Instance)
   5 from nmigen.cli import rtlil
   6
   7 class DummyPLL(Elaboratable):
   8     def __init__(self, instance):
   9         self.instance = instance
  10         self.clk_24_i = Signal(reset_less=True) # external incoming
  11         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
  12         self.clk_pll_o = Signal(reset_less=True)  # output clock
  13         self.pll_test_o = Signal(reset_less=True)  # test out
  14         self.pll_vco_o = Signal(reset_less=True) # analog
  15
  16     def elaborate(self, platform):
  17         m = Module()
  18
  19         if self.instance:
  20             clk_24_i = Signal(reset_less=True) # external incoming
  21             clk_sel_i = Signal(2, reset_less=True) # PLL selection
  22             clk_pll_o = Signal(reset_less=True)  # output clock
  23             pll_test_o = Signal(reset_less=True)  # test out
  24             pll_vco_o = Signal(reset_less=True) # analog
  25             pll = Instance("pll", i_ref=clk_24_i,
  26                                   i_a0=clk_sel_i[0],
  27                                   i_a1=clk_sel_i[1],
  28                                   o_out_v=clk_pll_o,
  29                                   o_div_out_test=pll_test_o,
  30                                   o_vco_test_ana=pll_vco_o,
  31                            )
  32             m.submodules['real_pll'] = pll
  33             #pll.attrs['blackbox'] = 1
  34             m.d.comb += clk_24_i.eq(self.clk_24_i)
  35             m.d.comb += clk_sel_i.eq(self.clk_sel_i)
  36             m.d.comb += self.clk_pll_o.eq(clk_pll_o)
  37             m.d.comb += self.pll_test_o.eq(pll_test_o)
  38             m.d.comb += self.pll_vco_o.eq(pll_vco_o)
  39
  40         else:
  41             m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
  42             # just get something, stops yosys destroying (optimising) these out
  43             with m.If(self.clk_sel_i == 0):
  44                 m.d.comb += self.pll_test_o.eq(self.clk_24_i)
  45                 m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
  46
  47         return m
  48
  49     def ports(self):
  50         return [self.clk_24_i, self.clk_sel_i, self.clk_pll_o,
  51                 self.pll_test_o, self.pll_vco_o]
  52
  53
  54 if __name__ == '__main__':
  55     dut = DummyPLL()
  56
  57     vl = rtlil.convert(dut, ports=dut.ports())
  58     with open("test_dummy_pll.il", "w") as f:
  59         f.write(vl)
  60