1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
51 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
52 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
53 with m
.If(insn
[20]): # field XFX.spr[-1] i think
54 comb
+= is_priv_insn
.eq(1)
58 class SPRMap(Elaboratable
):
59 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
63 self
.spr_i
= Signal(10, reset_less
=True)
64 self
.spr_o
= Data(SPR
, name
="spr_o")
65 self
.fast_o
= Data(3, name
="fast_o")
67 def elaborate(self
, platform
):
69 with m
.Switch(self
.spr_i
):
70 for i
, x
in enumerate(SPR
):
72 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
73 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
74 for x
, v
in spr_to_fast
.items():
76 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
77 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
81 class SVP64ExtraSpec(Elaboratable
):
82 """SVP64ExtraSpec - decodes SVP64 Extra specification.
84 selects the required EXTRA2/3 field.
86 see https://libre-soc.org/openpower/sv/svp64/
89 self
.extra
= Signal(9, reset_less
=True)
90 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
91 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
92 self
.spec
= Signal(3) # EXTRA spec for the register
94 def elaborate(self
, platform
):
99 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
100 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
101 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
102 # the register-extension information. extract those now
103 with m
.Switch(self
.etype
):
104 # 2-bit index selection mode
105 with m
.Case(SVEtype
.EXTRA2
):
106 with m
.Switch(self
.idx
):
107 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
108 comb
+= spec
[1:3].eq(self
.extra
[0:2])
109 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
110 comb
+= spec
[1:3].eq(self
.extra
[2:4])
111 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
112 comb
+= spec
[1:3].eq(self
.extra
[4:6])
113 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
114 comb
+= spec
[1:3].eq(self
.extra
[6:8])
115 # 3-bit index selection mode
116 with m
.Case(SVEtype
.EXTRA3
):
117 with m
.Switch(self
.idx
):
118 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
119 comb
+= spec
.eq(self
.extra
[0:3])
120 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
121 comb
+= spec
.eq(self
.extra
[3:6])
122 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
123 comb
+= spec
.eq(self
.extra
[6:9])
124 # cannot fit more than 9 bits so there is no 4th thing
129 class SVP64RegExtra(SVP64ExtraSpec
):
130 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
132 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
133 depending on info in one of the positions in the EXTRA field.
135 designed so that "no change" to the 5-bit register number occurs if
136 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
138 see https://libre-soc.org/openpower/sv/svp64/
141 SVP64ExtraSpec
.__init
__(self
)
142 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
143 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
144 self
.isvec
= Signal(1) # reg is marked as vector if true
146 def elaborate(self
, platform
):
147 m
= super().elaborate(platform
) # select required EXTRA2/3
150 # first get the spec. if not changed it's "scalar identity behaviour"
151 # which is zero which is ok.
154 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
155 # from above, which (by design) has the effect of "no change", below.
157 # simple: isvec is top bit of spec
158 comb
+= self
.isvec
.eq(spec
[2])
160 # decode vector differently from scalar
161 with m
.If(self
.isvec
):
162 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
163 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
165 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
166 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
171 class SVP64CRExtra(SVP64ExtraSpec
):
172 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
174 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
175 depending on info in one of the positions in the EXTRA field.
177 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
179 designed so that "no change" to the 3-bit CR register number occurs if
180 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
182 see https://libre-soc.org/openpower/sv/svp64/appendix
185 SVP64ExtraSpec
.__init
__(self
)
186 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
187 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
188 self
.isvec
= Signal(1) # reg is marked as vector if true
190 def elaborate(self
, platform
):
191 m
= super().elaborate(platform
) # select required EXTRA2/3
194 # first get the spec. if not changed it's "scalar identity behaviour"
195 # which is zero which is ok.
198 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
199 # from above, which (by design) has the effect of "no change", below.
201 # simple: isvec is top bit of spec
202 comb
+= self
.isvec
.eq(spec
[2])
204 # decode vector differently from scalar, insert bits 0 and 1 accordingly
205 with m
.If(self
.isvec
):
206 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
207 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec
[:2], self
.cr_in
))
209 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
210 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec
[:2]))
215 class DecodeA(Elaboratable
):
216 """DecodeA from instruction
218 decodes register RA, implicit and explicit CSRs
221 def __init__(self
, dec
):
223 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
224 self
.insn_in
= Signal(32, reset_less
=True)
225 self
.reg_out
= Data(5, name
="reg_a")
226 self
.spr_out
= Data(SPR
, "spr_a")
227 self
.fast_out
= Data(3, "fast_a")
229 def elaborate(self
, platform
):
234 m
.submodules
.sprmap
= sprmap
= SPRMap()
236 # select Register A field
237 ra
= Signal(5, reset_less
=True)
238 comb
+= ra
.eq(self
.dec
.RA
)
239 with m
.If((self
.sel_in
== In1Sel
.RA
) |
240 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
241 (ra
!= Const(0, 5)))):
242 comb
+= reg
.data
.eq(ra
)
245 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
246 # moved it to 1st position (in1_sel)... because
247 rs
= Signal(5, reset_less
=True)
248 comb
+= rs
.eq(self
.dec
.RS
)
249 with m
.If(self
.sel_in
== In1Sel
.RS
):
250 comb
+= reg
.data
.eq(rs
)
253 # decode Fast-SPR based on instruction type
254 with m
.Switch(op
.internal_op
):
256 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
257 with m
.Case(MicrOp
.OP_BC
):
258 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
260 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
261 comb
+= self
.fast_out
.ok
.eq(1)
262 with m
.Case(MicrOp
.OP_BCREG
):
263 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
264 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
265 with m
.If(xo9
& ~xo5
):
267 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 # MFSPR move from SPRs
271 with m
.Case(MicrOp
.OP_MFSPR
):
272 spr
= Signal(10, reset_less
=True)
273 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
274 comb
+= sprmap
.spr_i
.eq(spr
)
275 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
276 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
281 class DecodeAImm(Elaboratable
):
282 """DecodeA immediate from instruction
284 decodes register RA, whether immediate-zero, implicit and
288 def __init__(self
, dec
):
290 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
291 self
.immz_out
= Signal(reset_less
=True)
293 def elaborate(self
, platform
):
297 # zero immediate requested
298 ra
= Signal(5, reset_less
=True)
299 comb
+= ra
.eq(self
.dec
.RA
)
300 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
301 comb
+= self
.immz_out
.eq(1)
306 class DecodeB(Elaboratable
):
307 """DecodeB from instruction
309 decodes register RB, different forms of immediate (signed, unsigned),
310 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
311 by industry-standard convention, "lane 2" is where fully-decoded
312 immediates are muxed in.
315 def __init__(self
, dec
):
317 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
318 self
.insn_in
= Signal(32, reset_less
=True)
319 self
.reg_out
= Data(7, "reg_b")
320 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
321 self
.fast_out
= Data(3, "fast_b")
323 def elaborate(self
, platform
):
329 # select Register B field
330 with m
.Switch(self
.sel_in
):
331 with m
.Case(In2Sel
.RB
):
332 comb
+= reg
.data
.eq(self
.dec
.RB
)
334 with m
.Case(In2Sel
.RS
):
335 # for M-Form shiftrot
336 comb
+= reg
.data
.eq(self
.dec
.RS
)
339 # decode SPR2 based on instruction type
340 # BCREG implicitly uses LR or TAR for 2nd reg
341 # CTR however is already in fast_spr1 *not* 2.
342 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
343 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
344 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
346 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
347 comb
+= self
.fast_out
.ok
.eq(1)
349 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
350 comb
+= self
.fast_out
.ok
.eq(1)
355 class DecodeBImm(Elaboratable
):
356 """DecodeB immediate from instruction
358 def __init__(self
, dec
):
360 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
361 self
.imm_out
= Data(64, "imm_b")
363 def elaborate(self
, platform
):
367 # select Register B Immediate
368 with m
.Switch(self
.sel_in
):
369 with m
.Case(In2Sel
.CONST_UI
): # unsigned
370 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
371 comb
+= self
.imm_out
.ok
.eq(1)
372 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
373 si
= Signal(16, reset_less
=True)
374 comb
+= si
.eq(self
.dec
.SI
)
375 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
376 comb
+= self
.imm_out
.ok
.eq(1)
377 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
378 si_hi
= Signal(32, reset_less
=True)
379 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
380 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
381 comb
+= self
.imm_out
.ok
.eq(1)
382 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
383 ui
= Signal(16, reset_less
=True)
384 comb
+= ui
.eq(self
.dec
.UI
)
385 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
386 comb
+= self
.imm_out
.ok
.eq(1)
387 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
388 li
= Signal(26, reset_less
=True)
389 comb
+= li
.eq(self
.dec
.LI
<< 2)
390 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
391 comb
+= self
.imm_out
.ok
.eq(1)
392 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
393 bd
= Signal(16, reset_less
=True)
394 comb
+= bd
.eq(self
.dec
.BD
<< 2)
395 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
396 comb
+= self
.imm_out
.ok
.eq(1)
397 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
398 ds
= Signal(16, reset_less
=True)
399 comb
+= ds
.eq(self
.dec
.DS
<< 2)
400 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
401 comb
+= self
.imm_out
.ok
.eq(1)
402 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
403 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
404 comb
+= self
.imm_out
.ok
.eq(1)
405 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
406 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
407 comb
+= self
.imm_out
.ok
.eq(1)
408 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
409 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
410 comb
+= self
.imm_out
.ok
.eq(1)
415 class DecodeC(Elaboratable
):
416 """DecodeC from instruction
418 decodes register RC. this is "lane 3" into some CompUnits (not many)
421 def __init__(self
, dec
):
423 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
424 self
.insn_in
= Signal(32, reset_less
=True)
425 self
.reg_out
= Data(5, "reg_c")
427 def elaborate(self
, platform
):
433 # select Register C field
434 with m
.Switch(self
.sel_in
):
435 with m
.Case(In3Sel
.RB
):
436 # for M-Form shiftrot
437 comb
+= reg
.data
.eq(self
.dec
.RB
)
439 with m
.Case(In3Sel
.RS
):
440 comb
+= reg
.data
.eq(self
.dec
.RS
)
446 class DecodeOut(Elaboratable
):
447 """DecodeOut from instruction
449 decodes output register RA, RT or SPR
452 def __init__(self
, dec
):
454 self
.sel_in
= Signal(OutSel
, reset_less
=True)
455 self
.insn_in
= Signal(32, reset_less
=True)
456 self
.reg_out
= Data(5, "reg_o")
457 self
.spr_out
= Data(SPR
, "spr_o")
458 self
.fast_out
= Data(3, "fast_o")
460 def elaborate(self
, platform
):
463 m
.submodules
.sprmap
= sprmap
= SPRMap()
467 # select Register out field
468 with m
.Switch(self
.sel_in
):
469 with m
.Case(OutSel
.RT
):
470 comb
+= reg
.data
.eq(self
.dec
.RT
)
472 with m
.Case(OutSel
.RA
):
473 comb
+= reg
.data
.eq(self
.dec
.RA
)
475 with m
.Case(OutSel
.SPR
):
476 spr
= Signal(10, reset_less
=True)
477 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
478 # MFSPR move to SPRs - needs mapping
479 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
480 comb
+= sprmap
.spr_i
.eq(spr
)
481 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
482 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
485 with m
.Switch(op
.internal_op
):
487 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
488 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
489 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
491 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
492 comb
+= self
.fast_out
.ok
.eq(1)
494 # RFID 1st spr (fast)
495 with m
.Case(MicrOp
.OP_RFID
):
496 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
497 comb
+= self
.fast_out
.ok
.eq(1)
502 class DecodeOut2(Elaboratable
):
503 """DecodeOut2 from instruction
505 decodes output registers (2nd one). note that RA is *implicit* below,
506 which now causes problems with SVP64
508 TODO: SVP64 is a little more complex, here. svp64 allows extending
509 by one more destination by having one more EXTRA field. RA-as-src
510 is not the same as RA-as-dest. limited in that it's the same first
511 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
512 for operations that have src-as-dest: mostly this is LD/ST-with-update
513 but there are others.
516 def __init__(self
, dec
):
518 self
.sel_in
= Signal(OutSel
, reset_less
=True)
519 self
.lk
= Signal(reset_less
=True)
520 self
.insn_in
= Signal(32, reset_less
=True)
521 self
.reg_out
= Data(5, "reg_o2")
522 self
.fast_out
= Data(3, "fast_o2")
524 def elaborate(self
, platform
):
528 #m.submodules.svdec = svdec = SVP64RegExtra()
530 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
531 #reg = Signal(5, reset_less=True)
533 if hasattr(self
.dec
.op
, "upd"):
534 # update mode LD/ST uses read-reg A also as an output
535 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
536 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
537 comb
+= self
.reg_out
.ok
.eq(1)
539 # B, BC or BCREG: potential implicit register (LR) output
540 # these give bl, bcl, bclrl, etc.
541 with m
.Switch(op
.internal_op
):
543 # BC* implicit register (LR)
544 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
545 with m
.If(self
.lk
): # "link" mode
546 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
547 comb
+= self
.fast_out
.ok
.eq(1)
549 # RFID 2nd spr (fast)
550 with m
.Case(MicrOp
.OP_RFID
):
551 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
552 comb
+= self
.fast_out
.ok
.eq(1)
557 class DecodeRC(Elaboratable
):
558 """DecodeRc from instruction
560 decodes Record bit Rc
563 def __init__(self
, dec
):
565 self
.sel_in
= Signal(RC
, reset_less
=True)
566 self
.insn_in
= Signal(32, reset_less
=True)
567 self
.rc_out
= Data(1, "rc")
569 def elaborate(self
, platform
):
573 # select Record bit out field
574 with m
.Switch(self
.sel_in
):
576 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
577 comb
+= self
.rc_out
.ok
.eq(1)
579 comb
+= self
.rc_out
.data
.eq(1)
580 comb
+= self
.rc_out
.ok
.eq(1)
581 with m
.Case(RC
.NONE
):
582 comb
+= self
.rc_out
.data
.eq(0)
583 comb
+= self
.rc_out
.ok
.eq(1)
588 class DecodeOE(Elaboratable
):
589 """DecodeOE from instruction
591 decodes OE field: uses RC decode detection which might not be good
593 -- For now, use "rc" in the decode table to decide whether oe exists.
594 -- This is not entirely correct architecturally: For mulhd and
595 -- mulhdu, the OE field is reserved. It remains to be seen what an
596 -- actual POWER9 does if we set it on those instructions, for now we
597 -- test that further down when assigning to the multiplier oe input.
600 def __init__(self
, dec
):
602 self
.sel_in
= Signal(RC
, reset_less
=True)
603 self
.insn_in
= Signal(32, reset_less
=True)
604 self
.oe_out
= Data(1, "oe")
606 def elaborate(self
, platform
):
611 with m
.Switch(op
.internal_op
):
613 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
615 # XXX ARGH! ignoring OE causes incompatibility with microwatt
616 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
617 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
618 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
619 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
620 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
621 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
625 # all other ops decode OE field
627 # select OE bit out field
628 with m
.Switch(self
.sel_in
):
630 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
631 comb
+= self
.oe_out
.ok
.eq(1)
636 class DecodeCRIn(Elaboratable
):
637 """Decodes input CR from instruction
639 CR indices - insn fields - (not the data *in* the CR) require only 3
640 bits because they refer to CR0-CR7
643 def __init__(self
, dec
):
645 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
646 self
.insn_in
= Signal(32, reset_less
=True)
647 self
.cr_bitfield
= Data(3, "cr_bitfield")
648 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
649 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
650 self
.whole_reg
= Data(8, "cr_fxm")
652 def elaborate(self
, platform
):
656 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
659 # zero-initialisation
660 comb
+= self
.cr_bitfield
.ok
.eq(0)
661 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
662 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
663 comb
+= self
.whole_reg
.ok
.eq(0)
665 # select the relevant CR bitfields
666 with m
.Switch(self
.sel_in
):
667 with m
.Case(CRInSel
.NONE
):
668 pass # No bitfield activated
669 with m
.Case(CRInSel
.CR0
):
670 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
671 comb
+= self
.cr_bitfield
.ok
.eq(1)
672 with m
.Case(CRInSel
.BI
):
673 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
674 comb
+= self
.cr_bitfield
.ok
.eq(1)
675 with m
.Case(CRInSel
.BFA
):
676 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
677 comb
+= self
.cr_bitfield
.ok
.eq(1)
678 with m
.Case(CRInSel
.BA_BB
):
679 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
680 comb
+= self
.cr_bitfield
.ok
.eq(1)
681 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
682 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
683 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
684 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
685 with m
.Case(CRInSel
.BC
):
686 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
687 comb
+= self
.cr_bitfield
.ok
.eq(1)
688 with m
.Case(CRInSel
.WHOLE_REG
):
689 comb
+= self
.whole_reg
.ok
.eq(1)
690 move_one
= Signal(reset_less
=True)
691 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
692 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
693 # must one-hot the FXM field
694 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
695 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
697 # otherwise use all of it
698 comb
+= self
.whole_reg
.data
.eq(0xff)
703 class DecodeCROut(Elaboratable
):
704 """Decodes input CR from instruction
706 CR indices - insn fields - (not the data *in* the CR) require only 3
707 bits because they refer to CR0-CR7
710 def __init__(self
, dec
):
712 self
.rc_in
= Signal(reset_less
=True)
713 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
714 self
.insn_in
= Signal(32, reset_less
=True)
715 self
.cr_bitfield
= Data(3, "cr_bitfield")
716 self
.whole_reg
= Data(8, "cr_fxm")
718 def elaborate(self
, platform
):
722 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
725 comb
+= self
.cr_bitfield
.ok
.eq(0)
726 comb
+= self
.whole_reg
.ok
.eq(0)
728 with m
.Switch(self
.sel_in
):
729 with m
.Case(CROutSel
.NONE
):
730 pass # No bitfield activated
731 with m
.Case(CROutSel
.CR0
):
732 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
733 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
734 with m
.Case(CROutSel
.BF
):
735 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
736 comb
+= self
.cr_bitfield
.ok
.eq(1)
737 with m
.Case(CROutSel
.BT
):
738 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
739 comb
+= self
.cr_bitfield
.ok
.eq(1)
740 with m
.Case(CROutSel
.WHOLE_REG
):
741 comb
+= self
.whole_reg
.ok
.eq(1)
742 move_one
= Signal(reset_less
=True)
743 comb
+= move_one
.eq(self
.insn_in
[20])
744 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
746 # must one-hot the FXM field
747 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
748 with m
.If(ppick
.en_o
):
749 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
751 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
753 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
755 # otherwise use all of it
756 comb
+= self
.whole_reg
.data
.eq(0xff)
760 # dictionary of Input Record field names that, if they exist,
761 # will need a corresponding CSV Decoder file column (actually, PowerOp)
762 # to be decoded (this includes the single bit names)
763 record_names
= {'insn_type': 'internal_op',
764 'fn_unit': 'function_unit',
768 'imm_data': 'in2_sel',
769 'invert_in': 'inv_a',
770 'invert_out': 'inv_out',
773 'output_carry': 'cry_out',
774 'input_carry': 'cry_in',
775 'is_32bit': 'is_32b',
778 'data_len': 'ldst_len',
779 'byte_reverse': 'br',
780 'sign_extend': 'sgn_ext',
785 class PowerDecodeSubset(Elaboratable
):
786 """PowerDecodeSubset: dynamic subset decoder
788 only fields actually requested are copied over. hence, "subset" (duh).
790 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
792 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
795 self
.fn_name
= fn_name
797 opkls
= Decode2ToOperand
798 self
.do
= opkls(fn_name
)
799 col_subset
= self
.get_col_subset(self
.do
)
801 # only needed for "main" PowerDecode2
803 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
805 # create decoder if one not already given
807 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
808 row_subset
=self
.rowsubsetfn
)
811 # state information needed by the Decoder
813 state
= CoreState("dec2")
816 def get_col_subset(self
, do
):
817 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
818 for k
, v
in record_names
.items():
821 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
824 def rowsubsetfn(self
, opcode
, row
):
825 return row
['unit'] == self
.fn_name
828 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
830 def needs_field(self
, field
, op_field
):
835 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
837 def do_copy(self
, field
, val
, final
=False):
838 if final
or self
.final
:
842 if hasattr(do
, field
) and val
is not None:
843 return getattr(do
, field
).eq(val
)
846 def op_get(self
, op_field
):
847 return getattr(self
.dec
.op
, op_field
, None)
849 def elaborate(self
, platform
):
853 op
, do
= self
.dec
.op
, self
.do
854 msr
, cia
= state
.msr
, state
.pc
856 # fill in for a normal instruction (not an exception)
857 # copy over if non-exception, non-privileged etc. is detected
859 if self
.fn_name
is None:
862 name
= self
.fn_name
+ "tmp"
863 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
865 # set up submodule decoders
866 m
.submodules
.dec
= self
.dec
867 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
868 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
869 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
870 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
872 # copy instruction through...
874 dec_rc
.insn_in
, dec_oe
.insn_in
,
875 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
876 comb
+= i
.eq(self
.dec
.opcode_in
)
878 # ...and subdecoders' input fields
879 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
880 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
881 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
882 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
883 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
886 comb
+= self
.do_copy("msr", msr
)
887 comb
+= self
.do_copy("cia", cia
)
889 # set up instruction type
890 # no op: defaults to OP_ILLEGAL
891 if self
.fn_name
=="MMU":
892 # mmu is special case: needs SPR opcode as well
893 mmu0
= self
.mmu0_spr_dec
894 with m
.If(((mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
895 (mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
))):
896 comb
+= self
.do_copy("insn_type", mmu0
.op_get("internal_op"))
898 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
900 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
902 # function unit for decoded instruction: requires minor redirect
904 fn
= self
.op_get("function_unit")
905 spr
= Signal(10, reset_less
=True)
906 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
908 SPR_PID
= 48 # TODO read docs for POWER9
909 # Microwatt doesn't implement the partition table
910 # instead has PRTBL register (SPR) to point to process table
911 SPR_PRTBL
= 720 # see common.vhdl in microwatt, not in POWER9
912 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
913 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
914 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
)
915 |
(spr
==SPR_PRTBL
) |
(spr
==SPR_PID
))):
916 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
918 comb
+= self
.do_copy("fn_unit",fn
)
921 if self
.needs_field("zero_a", "in1_sel"):
922 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
923 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
924 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
925 if self
.needs_field("imm_data", "in2_sel"):
926 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
927 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
928 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
931 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
932 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
935 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
936 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
937 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
939 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
940 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
942 # decoded/selected instruction flags
943 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
944 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
945 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
946 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
947 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
948 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
949 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
950 lk
= self
.op_get("lk")
953 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
955 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
956 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
957 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
962 class PowerDecode2(PowerDecodeSubset
):
963 """PowerDecode2: the main instruction decoder.
965 whilst PowerDecode is responsible for decoding the actual opcode, this
966 module encapsulates further specialist, sparse information and
967 expansion of fields that is inconvenient to have in the CSV files.
968 for example: the encoding of the immediates, which are detected
969 and expanded out to their full value from an annotated (enum)
972 implicit register usage is also set up, here. for example: OP_BC
973 requires implicitly reading CTR, OP_RFID requires implicitly writing
976 in addition, PowerDecoder2 is responsible for detecting whether
977 instructions are illegal (or privileged) or not, and instead of
978 just leaving at that, *replacing* the instruction to execute with
979 a suitable alternative (trap).
981 LDSTExceptions are done the cycle _after_ they're detected (after
982 they come out of LDSTCompUnit). basically despite the instruction
983 being decoded, the results of the decode are completely ignored
984 and "exception.happened" used to set the "actual" instruction to
985 "OP_TRAP". the LDSTException data structure gets filled in,
986 in the CompTrapOpSubset and that's what it fills in SRR.
988 to make this work, TestIssuer must notice "exception.happened"
989 after the (failed) LD/ST and copies the LDSTException info from
990 the output, into here (PowerDecoder2). without incrementing PC.
993 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
994 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
995 self
.exc
= LDSTException("dec2_exc")
997 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
998 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
999 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1000 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1001 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1002 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1003 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1004 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1005 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1006 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs are vectors
1008 def get_col_subset(self
, opkls
):
1009 subset
= super().get_col_subset(opkls
)
1010 subset
.add("asmcode")
1011 subset
.add("in1_sel")
1012 subset
.add("in2_sel")
1013 subset
.add("in3_sel")
1014 subset
.add("out_sel")
1015 subset
.add("sv_in1")
1016 subset
.add("sv_in2")
1017 subset
.add("sv_in3")
1018 subset
.add("sv_out")
1019 subset
.add("sv_cr_in")
1020 subset
.add("sv_cr_out")
1021 subset
.add("SV_Etype")
1022 subset
.add("SV_Ptype")
1024 subset
.add("internal_op")
1028 def elaborate(self
, platform
):
1029 m
= super().elaborate(platform
)
1032 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1033 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1037 # fill in for a normal instruction (not an exception)
1038 # copy over if non-exception, non-privileged etc. is detected
1040 # set up submodule decoders
1041 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1042 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1043 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1044 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1045 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1047 # and SVP64 Extra decoders
1048 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1049 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1050 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1051 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1052 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1053 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1054 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1055 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1056 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1058 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1059 reg
= Signal(5, reset_less
=True)
1061 # copy instruction through...
1062 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1063 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1064 comb
+= i
.eq(self
.dec
.opcode_in
)
1066 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1067 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1068 # which in turn were auto-generated by sv_analysis.py
1069 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1073 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1074 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1077 # CR in - index selection slightly different due to shared CR field sigh
1078 cr_a_idx
= Signal(SVEXTRA
)
1079 cr_b_idx
= Signal(SVEXTRA
)
1081 # these change slightly, when decoding BA/BB. really should have
1082 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1083 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1084 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1085 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1086 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1087 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1089 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1090 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1091 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1093 # indices are slightly different, BA/BB mess sorted above
1094 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1095 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1096 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1098 # ...and subdecoders' input fields
1099 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1100 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1101 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1102 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1103 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1104 if hasattr(do
, "lk"):
1105 comb
+= dec_o2
.lk
.eq(do
.lk
)
1107 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1108 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1109 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1111 # registers a, b, c and out and out2 (LD/ST EA)
1112 for to_reg
, fromreg
, svdec
in (
1113 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1114 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1115 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1116 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1117 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1118 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1119 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1120 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1121 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1122 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1123 # this trick only holds when elwidth=default and in single-pred
1124 with m
.If(svdec
.isvec
):
1125 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1127 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1129 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1130 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1131 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1132 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1133 # XXX TODO - work out where this should come from. the problem is
1134 # that LD-with-update is implied (computed from "is instruction in
1135 # "update mode" rather than specified cleanly as its own CSV column
1136 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1138 # output reg-is-vectorised (and when no output is vectorised)
1139 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1140 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1141 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1142 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1143 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1144 # TODO: include SPRs and CRs here! must be True when *all* are scalar
1145 comb
+= self
.no_out_vec
.eq((~o2_svdec
.isvec
) & (~o_svdec
.isvec
))
1148 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1149 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1152 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1153 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1154 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1155 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1157 # condition registers (CR)
1158 for to_reg
, fromreg
, svdec
in (
1159 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
, crin_svdec
),
1160 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
, crin_svdec_b
),
1161 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
, crin_svdec_o
),
1162 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
, crout_svdec
)):
1163 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1164 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1165 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1166 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1167 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1169 # sigh this is exactly the sort of thing for which the
1170 # decoder is designed to not need. MTSPR, MFSPR and others need
1171 # access to the XER bits. however setting e.oe is not appropriate
1172 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1173 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1174 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1175 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1176 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1177 comb
+= e
.xer_out
.eq(1)
1179 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1180 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1181 # *DO NOT* call self.trap here. that would reset absolutely
1182 # everything including destroying read of RA and RB.
1183 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1185 ####################
1186 # ok so the instruction's been decoded, blah blah, however
1187 # now we need to determine if it's actually going to go ahead...
1188 # *or* if in fact it's a privileged operation, whether there's
1189 # an external interrupt, etc. etc. this is a simple priority
1190 # if-elif-elif sequence. decrement takes highest priority,
1191 # EINT next highest, privileged operation third.
1193 # check if instruction is privileged
1194 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1196 # different IRQ conditions
1197 ext_irq_ok
= Signal()
1198 dec_irq_ok
= Signal()
1203 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1204 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1205 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1206 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1208 # LD/ST exceptions. TestIssuer copies the exception info at us
1209 # after a failed LD/ST.
1210 with m
.If(exc
.happened
):
1211 with m
.If(exc
.alignment
):
1212 self
.trap(m
, TT
.PRIV
, 0x600)
1213 with m
.Elif(exc
.instr_fault
):
1214 with m
.If(exc
.segment_fault
):
1215 self
.trap(m
, TT
.PRIV
, 0x480)
1217 # pass exception info to trap to create SRR1
1218 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1220 with m
.If(exc
.segment_fault
):
1221 self
.trap(m
, TT
.PRIV
, 0x380)
1223 self
.trap(m
, TT
.PRIV
, 0x300)
1225 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1226 with m
.Elif(dec_irq_ok
):
1227 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1229 # external interrupt? only if MSR.EE set
1230 with m
.Elif(ext_irq_ok
):
1231 self
.trap(m
, TT
.EINT
, 0x500)
1233 # privileged instruction trap
1234 with m
.Elif(priv_ok
):
1235 self
.trap(m
, TT
.PRIV
, 0x700)
1237 # illegal instruction must redirect to trap. this is done by
1238 # *overwriting* the decoded instruction and starting again.
1239 # (note: the same goes for interrupts and for privileged operations,
1240 # just with different trapaddr and traptype)
1241 with m
.Elif(illeg_ok
):
1242 # illegal instruction trap
1243 self
.trap(m
, TT
.ILLEG
, 0x700)
1245 # no exception, just copy things to the output
1249 ####################
1250 # follow-up after trap/irq to set up SRR0/1
1252 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1253 # Note: OP_SC could actually be modified to just be a trap
1254 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1255 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1256 # TRAP write fast1 = SRR0
1257 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1258 comb
+= e_out
.write_fast1
.ok
.eq(1)
1259 # TRAP write fast2 = SRR1
1260 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1261 comb
+= e_out
.write_fast2
.ok
.eq(1)
1263 # RFID: needs to read SRR0/1
1264 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1265 # TRAP read fast1 = SRR0
1266 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1267 comb
+= e_out
.read_fast1
.ok
.eq(1)
1268 # TRAP read fast2 = SRR1
1269 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1270 comb
+= e_out
.read_fast2
.ok
.eq(1)
1272 # annoying simulator bug
1273 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1274 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1278 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1279 """trap: this basically "rewrites" the decoded instruction as a trap
1282 op
, e
= self
.dec
.op
, self
.e
1283 comb
+= e
.eq(0) # reset eeeeeverything
1286 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1287 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1288 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1289 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1290 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1291 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1292 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1293 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1296 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
1297 # identifies if an instruction is a SVP64-encoded prefix, and extracts
1298 # the 24-bit SVP64 context (RM) if it is
1299 class SVP64PrefixDecoder(Elaboratable
):
1302 self
.opcode_in
= Signal(32, reset_less
=True)
1303 self
.raw_opcode_in
= Signal
.like(self
.opcode_in
, reset_less
=True)
1304 self
.is_svp64_mode
= Signal(1, reset_less
=True)
1305 self
.svp64_rm
= Signal(24, reset_less
=True)
1306 self
.bigendian
= Signal(reset_less
=True)
1308 def elaborate(self
, platform
):
1311 # sigh copied this from TopPowerDecoder
1312 # raw opcode in assumed to be in LE order: byte-reverse it to get BE
1313 raw_le
= self
.raw_opcode_in
1315 for i
in range(0, 32, 8):
1316 l
.append(raw_le
[i
:i
+8])
1319 comb
+= self
.opcode_in
.eq(Mux(self
.bigendian
, raw_be
, raw_le
))
1321 # start identifying if the incoming opcode is SVP64 prefix)
1322 major
= Signal(6, reset_less
=True)
1324 comb
+= major
.eq(self
.opcode_in
[26:32])
1325 comb
+= self
.is_svp64_mode
.eq((major
== Const(1, 6)) & # EXT01
1326 self
.opcode_in
[31-7] & # identifier
1327 self
.opcode_in
[31-9]) # bits
1329 # now grab the 24-bit ReMap context bits,
1330 rmfields
= [6, 8] + list(range(10,32)) # SVP64 24-bit RM
1332 for idx
in rmfields
:
1333 l
.append(self
.opcode_in
[31-idx
])
1334 with m
.If(self
.is_svp64_mode
):
1335 comb
+= self
.svp64_rm
.eq(Cat(*l
))
1340 return [self
.opcode_in
, self
.raw_opcode_in
, self
.is_svp64_mode
,
1341 self
.svp64_rm
, self
.bigendian
]
1343 def get_rdflags(e
, cu
):
1345 for idx
in range(cu
.n_src
):
1346 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1347 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1349 print("rdflags", rdl
)
1353 if __name__
== '__main__':
1354 svp64
= SVP64PowerDecoder()
1355 vl
= rtlil
.convert(svp64
, ports
=svp64
.ports())
1356 with
open("svp64_dec.il", "w") as f
:
1358 pdecode
= create_pdecode()
1359 dec2
= PowerDecode2(pdecode
)
1360 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1361 with
open("dec2.il", "w") as f
: