1 from nmigen
import Signal
, Const
2 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
3 from soc
.fu
.shift_rot
.sr_input_record
import CompSROpSubset
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
6 from soc
.fu
.logical
.pipe_data
import LogicalOutputData
7 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
10 class ShiftRotInputData(IntegerData
):
11 regspec
= [('INT', 'a', '0:63'),
12 ('INT', 'rb', '0:63'),
13 ('INT', 'rs', '0:63'),
14 ('XER', 'xer_ca', '34,45')]
15 def __init__(self
, pspec
):
16 super().__init
__(pspec
)
17 self
.a
= Signal(64, reset_less
=True) # RA
18 self
.rb
= Signal(64, reset_less
=True) # RB/immediate
19 self
.rs
= Signal(64, reset_less
=True) # RS
20 self
.xer_ca
= Signal(2, reset_less
=True) # XER bit 34/45: CA/CA32
23 yield from super().__iter
__()
31 return lst
+ [self
.rs
.eq(i
.rs
), self
.a
.eq(i
.a
),
33 self
.xer_ca
.eq(i
.xer_ca
) ]
36 class ShiftRotPipeSpec(CommonPipeSpec
):
37 regspec
= (ShiftRotInputData
.regspec
, LogicalOutputData
.regspec
)
38 opsubsetkls
= CompSROpSubset