Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / shift_rot / pipe_data.py
1 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
2 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
3 from soc.fu.alu.pipe_data import ALUOutputData
4
5
6 class ShiftRotInputData(FUBaseData):
7 def __init__(self, pspec):
8 super().__init__(pspec, False)
9 # convenience
10 self.a, self.b, self.rs = self.ra, self.rb, self.rc
11
12 @property
13 def regspec(self):
14 return [('INT', 'ra', self.intrange), # RA
15 ('INT', 'rb', self.intrange), # RB/immediate
16 ('INT', 'rc', self.intrange), # RB/immediate
17 ('XER', 'xer_so', '32'), # XER bit 32: SO
18 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
19
20
21 # input to shiftrot final stage (common output)
22 class ShiftRotOutputData(FUBaseData):
23 def __init__(self, pspec):
24 super().__init__(pspec, True)
25 # convenience
26 self.cr0 = self.cr_a
27
28 @property
29 def regspec(self):
30 return [('INT', 'o', self.intrange),
31 ('CR', 'cr_a', '0:3'),
32 ('XER', 'xer_so', '32'), # bit0: so
33 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
34 ]
35
36
37 # output from shiftrot final stage (common output) - note that XER.so
38 # is *not* included (the only reason it's in the input is because of CR0)
39 class ShiftRotOutputDataFinal(FUBaseData):
40 def __init__(self, pspec):
41 super().__init__(pspec, True)
42 # convenience
43 self.cr0 = self.cr_a
44
45 @property
46 def regspec(self):
47 return [('INT', 'o', self.intrange),
48 ('CR', 'cr_a', '0:3'),
49 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
50 ]
51
52
53 class ShiftRotPipeSpec(CommonPipeSpec):
54 regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal)
55 opsubsetkls = CompSROpSubset