1 from soc
.fu
.shift_rot
.sr_input_record
import CompSROpSubset
2 from soc
.fu
.pipe_data
import FUBaseData
, CommonPipeSpec
3 from soc
.fu
.alu
.pipe_data
import ALUOutputData
6 class ShiftRotInputData(FUBaseData
):
7 def __init__(self
, pspec
):
8 super().__init
__(pspec
, False)
10 self
.a
, self
.b
, self
.rs
= self
.ra
, self
.rb
, self
.rc
14 return [('INT', 'ra', self
.intrange
), # RA
15 ('INT', 'rb', self
.intrange
), # RB/immediate
16 ('INT', 'rc', self
.intrange
), # RB/immediate
17 ('XER', 'xer_so', '32'), # XER bit 32: SO
18 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
21 # input to shiftrot final stage (common output)
22 class ShiftRotOutputData(FUBaseData
):
23 def __init__(self
, pspec
):
24 super().__init
__(pspec
, True)
30 return [('INT', 'o', self
.intrange
),
31 ('CR', 'cr_a', '0:3'),
32 ('XER', 'xer_so', '32'), # bit0: so
33 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
37 # output from shiftrot final stage (common output) - note that XER.so
38 # is *not* included (the only reason it's in the input is because of CR0)
39 class ShiftRotOutputDataFinal(FUBaseData
):
40 def __init__(self
, pspec
):
41 super().__init
__(pspec
, True)
47 return [('INT', 'o', self
.intrange
),
48 ('CR', 'cr_a', '0:3'),
49 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
53 class ShiftRotPipeSpec(CommonPipeSpec
):
54 regspecklses
= (ShiftRotInputData
, ShiftRotOutputDataFinal
)
55 opsubsetkls
= CompSROpSubset