1 from soc
.fu
.shift_rot
.sr_input_record
import CompSROpSubset
2 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
3 from soc
.fu
.alu
.pipe_data
import ALUOutputData
6 class ShiftRotInputData(IntegerData
):
7 regspec
= [('INT', 'ra', '0:63'), # RA
8 ('INT', 'rb', '0:63'), # RB
9 ('INT', 'rc', '0:63'), # RS
10 ('XER', 'xer_so', '32'), # XER bit 32: SO
11 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
12 def __init__(self
, pspec
):
13 super().__init
__(pspec
, False)
15 self
.a
, self
.b
, self
.rs
= self
.ra
, self
.rb
, self
.rc
18 # sigh although ShiftRot never changes xer_ov it is just easier
19 # right now to have it. also SO never gets changed, although it
20 # is an input (to create CR). really need something similar to
21 # MulOutputData which has xer_so yet derives from LogicalOutputData
22 class ShiftRotPipeSpec(CommonPipeSpec
):
23 regspec
= (ShiftRotInputData
.regspec
, ALUOutputData
.regspec
)
24 opsubsetkls
= CompSROpSubset