1 from soc
.fu
.shift_rot
.sr_input_record
import CompSROpSubset
2 from soc
.fu
.pipe_data
import FUBaseData
, CommonPipeSpec
3 from soc
.fu
.alu
.pipe_data
import ALUOutputData
6 class ShiftRotInputData(FUBaseData
):
7 regspec
= [('INT', 'ra', '0:63'), # RA
8 ('INT', 'rb', '0:63'), # RB
9 ('INT', 'rc', '0:63'), # RS
10 ('XER', 'xer_so', '32'), # XER bit 32: SO
11 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
12 def __init__(self
, pspec
):
13 super().__init
__(pspec
, False)
15 self
.a
, self
.b
, self
.rs
= self
.ra
, self
.rb
, self
.rc
18 # input to shiftrot final stage (common output)
19 class ShiftRotOutputData(FUBaseData
):
20 regspec
= [('INT', 'o', '0:63'), # RT
21 ('CR', 'cr_a', '0:3'),
22 ('XER', 'xer_so', '32'), # bit0: so
23 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
25 def __init__(self
, pspec
):
26 super().__init
__(pspec
, True)
31 # output from shiftrot final stage (common output) - note that XER.so
32 # is *not* included (the only reason it's in the input is because of CR0)
33 class ShiftRotOutputDataFinal(FUBaseData
):
34 regspec
= [('INT', 'o', '0:63'), # RT
35 ('CR', 'cr_a', '0:3'),
36 ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
38 def __init__(self
, pspec
):
39 super().__init
__(pspec
, True)
44 class ShiftRotPipeSpec(CommonPipeSpec
):
45 regspec
= (ShiftRotInputData
.regspec
, ShiftRotOutputDataFinal
.regspec
)
46 opsubsetkls
= CompSROpSubset