3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
23 from nmigen
.cli
import rtlil
25 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
29 from nmutil
.picker
import PriorityPicker
30 from nmutil
.util
import treereduce
32 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
33 from soc
.regfile
.regfiles
import RegFiles
34 from openpower
.decoder
.decode2execute1
import Decode2ToExecute1Type
35 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
36 from openpower
.decoder
.power_decoder2
import get_rdflags
37 from openpower
.decoder
.decode2execute1
import Data
38 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
39 from soc
.config
.test
.test_loadstore
import TestMemPspec
40 from openpower
.decoder
.power_enums
import MicrOp
41 from soc
.config
.state
import CoreState
45 from nmutil
.util
import rising_edge
48 # helper function for reducing a list of signals down to a parallel
50 def ortreereduce(tree
, attr
="data_o"):
51 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
54 def ortreereduce_sig(tree
):
55 return treereduce(tree
, operator
.or_
, lambda x
: x
)
58 # helper function to place full regs declarations first
59 def sort_fuspecs(fuspecs
):
61 for (regname
, fspec
) in fuspecs
.items():
62 if regname
.startswith("full"):
63 res
.append((regname
, fspec
))
64 for (regname
, fspec
) in fuspecs
.items():
65 if not regname
.startswith("full"):
66 res
.append((regname
, fspec
))
67 return res
# enumerate(res)
70 class NonProductionCore(Elaboratable
):
71 def __init__(self
, pspec
):
74 # test is SVP64 is to be enabled
75 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
77 # test to see if regfile ports should be reduced
78 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
79 (pspec
.regreduce
== True))
81 # single LD/ST funnel for memory access
82 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
83 pi
= self
.l0
.l0
.dports
[0]
85 # function units (only one each)
86 # only include mmu if enabled in pspec
87 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
89 # register files (yes plural)
90 self
.regs
= RegFiles(pspec
)
92 # instruction decoder - needs a Trap-capable Record (captures EINT etc.)
93 self
.e
= Decode2ToExecute1Type("core", opkls
=IssuerDecode2ToOperand
,
94 regreduce_en
=self
.regreduce_en
)
96 # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
97 self
.sv_a_nz
= Signal()
99 # state and raw instruction
100 self
.state
= CoreState("core")
101 self
.raw_insn_i
= Signal(32) # raw instruction
102 self
.bigendian_i
= Signal() # bigendian - TODO, set by MSR.BE
104 # issue/valid/busy signalling
105 self
.ivalid_i
= Signal(reset_less
=True) # instruction is valid
106 self
.issue_i
= Signal(reset_less
=True)
107 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
109 # start/stop and terminated signalling
110 self
.core_terminate_o
= Signal(reset
=0) # indicates stopped
112 # create per-FU instruction decoders (subsetted)
116 for funame
, fu
in self
.fus
.fus
.items():
117 f_name
= fu
.fnunit
.name
118 fnunit
= fu
.fnunit
.value
119 opkls
= fu
.opsubsetkls
121 self
.trapunit
= funame
123 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
126 svp64_en
=self
.svp64_en
,
127 regreduce_en
=self
.regreduce_en
)
128 self
.des
[funame
] = self
.decoders
[funame
].do
130 if "mmu0" in self
.decoders
:
131 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
133 def elaborate(self
, platform
):
135 # for testing purposes, to cut down on build time in coriolis2
136 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
137 x
= Signal() # dummy signal
142 m
.submodules
.fus
= self
.fus
143 m
.submodules
.l0
= l0
= self
.l0
144 self
.regs
.elaborate_into(m
, platform
)
149 for k
, v
in self
.decoders
.items():
150 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
151 comb
+= v
.dec
.raw_opcode_in
.eq(self
.raw_insn_i
)
152 comb
+= v
.dec
.bigendian
.eq(self
.bigendian_i
)
153 # sigh due to SVP64 RA_OR_ZERO detection connect these too
154 comb
+= v
.sv_a_nz
.eq(self
.sv_a_nz
)
156 # ssh, cheat: trap uses the main decoder because of the rewriting
157 self
.des
[self
.trapunit
] = self
.e
.do
159 # connect up Function Units, then read/write ports
160 fu_bitdict
= self
.connect_instruction(m
)
161 self
.connect_rdports(m
, fu_bitdict
)
162 self
.connect_wrports(m
, fu_bitdict
)
166 def connect_instruction(self
, m
):
167 """connect_instruction
169 uses decoded (from PowerOp) function unit information from CSV files
170 to ascertain which Function Unit should deal with the current
173 some (such as OP_ATTN, OP_NOP) are dealt with here, including
174 ignoring it and halting the processor. OP_NOP is a bit annoying
175 because the issuer expects busy flag still to be raised then lowered.
176 (this requires a fake counter to be set).
178 comb
, sync
= m
.d
.comb
, m
.d
.sync
181 # enable-signals for each FU, get one bit for each FU (by name)
182 fu_enable
= Signal(len(fus
), reset_less
=True)
184 for i
, funame
in enumerate(fus
.keys()):
185 fu_bitdict
[funame
] = fu_enable
[i
]
187 # enable the required Function Unit based on the opcode decode
188 # note: this *only* works correctly for simple core when one and
189 # *only* one FU is allocated per instruction
190 for funame
, fu
in fus
.items():
191 fnunit
= fu
.fnunit
.value
192 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
193 comb
+= enable
.eq((self
.e
.do
.fn_unit
& fnunit
).bool())
194 comb
+= fu_bitdict
[funame
].eq(enable
)
196 # sigh - need a NOP counter
198 with m
.If(counter
!= 0):
199 sync
+= counter
.eq(counter
- 1)
200 comb
+= self
.busy_o
.eq(1)
202 with m
.If(self
.ivalid_i
): # run only when valid
203 with m
.Switch(self
.e
.do
.insn_type
):
204 # check for ATTN: halt if true
205 with m
.Case(MicrOp
.OP_ATTN
):
206 m
.d
.sync
+= self
.core_terminate_o
.eq(1)
208 with m
.Case(MicrOp
.OP_NOP
):
209 sync
+= counter
.eq(2)
210 comb
+= self
.busy_o
.eq(1)
213 # connect up instructions. only one enabled at a time
214 for funame
, fu
in fus
.items():
215 do
= self
.des
[funame
]
216 enable
= fu_bitdict
[funame
]
218 # run this FunctionUnit if enabled
219 # route op, issue, busy, read flags and mask to FU
221 # operand comes from the *local* decoder
222 comb
+= fu
.oper_i
.eq_from(do
)
223 #comb += fu.oper_i.eq_from_execute1(e)
224 comb
+= fu
.issue_i
.eq(self
.issue_i
)
225 comb
+= self
.busy_o
.eq(fu
.busy_o
)
226 # rdmask, which is for registers, needs to come
227 # from the *main* decoder
228 rdmask
= get_rdflags(self
.e
, fu
)
229 comb
+= fu
.rdmaskn
.eq(~rdmask
)
233 def connect_rdport(self
, m
, fu_bitdict
, rdpickers
, regfile
, regname
, fspec
):
234 comb
, sync
= m
.d
.comb
, m
.d
.sync
240 # select the required read port. these are pre-defined sizes
241 rfile
= regs
.rf
[regfile
.lower()]
242 rport
= rfile
.r_ports
[rpidx
]
243 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
247 if not isinstance(fspecs
, list):
254 for i
, fspec
in enumerate(fspecs
):
255 # get the regfile specs for this regfile port
256 (rf
, read
, write
, wid
, fuspec
) = fspec
257 print ("fpsec", i
, fspec
, len(fuspec
))
258 ppoffs
.append(pplen
) # record offset for picker
260 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
261 rdflag
= Signal(name
=name
, reset_less
=True)
262 comb
+= rdflag
.eq(rf
)
263 rdflags
.append(rdflag
)
266 print ("pplen", pplen
)
268 # create a priority picker to manage this port
269 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
270 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
274 for i
, fspec
in enumerate(fspecs
):
275 (rf
, read
, write
, wid
, fuspec
) = fspec
276 # connect up the FU req/go signals, and the reg-read to the FU
277 # and create a Read Broadcast Bus
278 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
281 # connect request-read to picker input, and output to go-rd
282 fu_active
= fu_bitdict
[funame
]
283 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
284 addr_en
= Signal
.like(reads
[i
], name
="addr_en_"+name
)
285 pick
= Signal(name
="pick_"+name
) # picker input
286 rp
= Signal(name
="rp_"+name
) # picker output
287 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
289 # exclude any currently-enabled read-request (mask out active)
290 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
292 comb
+= rdpick
.i
[pi
].eq(pick
)
293 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
295 # if picked, select read-port "reg select" number to port
296 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
297 sync
+= delay_pick
.eq(rp
) # delayed "pick"
298 comb
+= addr_en
.eq(Mux(rp
, reads
[i
], 0))
300 # the read-enable happens combinatorially (see mux-bus below)
301 # but it results in the data coming out on a one-cycle delay.
305 addrs
.append(addr_en
)
308 # use the *delayed* pick signal to put requested data onto bus
309 with m
.If(delay_pick
):
310 # connect regfile port to input, creating fan-out Bus
312 print("reg connect widths",
313 regfile
, regname
, pi
, funame
,
314 src
.shape(), rport
.data_o
.shape())
315 # all FUs connect to same port
316 comb
+= src
.eq(rport
.data_o
)
318 # or-reduce the muxed read signals
320 # for unary-addressed
321 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
323 # for binary-addressed
324 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
325 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
326 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
328 def connect_rdports(self
, m
, fu_bitdict
):
329 """connect read ports
331 orders the read regspecs into a dict-of-dicts, by regfile, by
332 regport name, then connects all FUs that want that regport by
333 way of a PriorityPicker.
335 comb
, sync
= m
.d
.comb
, m
.d
.sync
339 # dictionary of lists of regfile read ports
340 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
342 # okaay, now we need a PriorityPicker per regfile per regfile port
343 # loootta pickers... peter piper picked a pack of pickled peppers...
345 for regfile
, spec
in byregfiles_rd
.items():
346 fuspecs
= byregfiles_rdspec
[regfile
]
347 rdpickers
[regfile
] = {}
349 # argh. an experiment to merge RA and RB in the INT regfile
350 # (we have too many read/write ports)
351 if self
.regreduce_en
:
353 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
354 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
355 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
356 if regfile
== 'FAST':
357 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
358 if 'fast2' in fuspecs
:
359 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
361 # for each named regfile port, connect up all FUs to that port
362 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
363 print("connect rd", regname
, fspec
)
364 self
.connect_rdport(m
, fu_bitdict
, rdpickers
, regfile
,
367 def connect_wrport(self
, m
, fu_bitdict
, wrpickers
, regfile
, regname
, fspec
):
368 comb
, sync
= m
.d
.comb
, m
.d
.sync
372 print("connect wr", regname
, fspec
)
375 # select the required write port. these are pre-defined sizes
376 print(regfile
, regs
.rf
.keys())
377 rfile
= regs
.rf
[regfile
.lower()]
378 wport
= rfile
.w_ports
[rpidx
]
381 if not isinstance(fspecs
, list):
387 for i
, fspec
in enumerate(fspecs
):
388 # get the regfile specs for this regfile port
389 (rf
, read
, write
, wid
, fuspec
) = fspec
390 print ("fpsec", i
, fspec
, len(fuspec
))
391 ppoffs
.append(pplen
) # record offset for picker
394 # create a priority picker to manage this port
395 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
396 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
401 for i
, fspec
in enumerate(fspecs
):
402 # connect up the FU req/go signals and the reg-read to the FU
403 # these are arbitrated by Data.ok signals
404 (rf
, read
, write
, wid
, fuspec
) = fspec
405 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
408 # write-request comes from dest.ok
409 dest
= fu
.get_out(idx
)
410 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
411 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
412 wrflag
= Signal(name
=name
, reset_less
=True)
413 comb
+= wrflag
.eq(dest
.ok
& fu
.busy_o
)
415 # connect request-write to picker input, and output to go-wr
416 fu_active
= fu_bitdict
[funame
]
417 pick
= fu
.wr
.rel_o
[idx
] & fu_active
# & wrflag
418 comb
+= wrpick
.i
[pi
].eq(pick
)
419 # create a single-pulse go write from the picker output
421 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
422 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
424 # connect the regspec write "reg select" number to this port
425 # only if one FU actually requests (and is granted) the port
426 # will the write-enable be activated
427 addr_en
= Signal
.like(write
)
429 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
430 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
434 addrs
.append(addr_en
)
437 # connect regfile port to input
438 print("reg connect widths",
439 regfile
, regname
, pi
, funame
,
440 dest
.shape(), wport
.data_i
.shape())
441 wsigs
.append(fu_dest_latch
)
443 # here is where we create the Write Broadcast Bus. simple, eh?
444 comb
+= wport
.data_i
.eq(ortreereduce_sig(wsigs
))
446 # for unary-addressed
447 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
449 # for binary-addressed
450 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
451 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
453 def connect_wrports(self
, m
, fu_bitdict
):
454 """connect write ports
456 orders the write regspecs into a dict-of-dicts, by regfile,
457 by regport name, then connects all FUs that want that regport
458 by way of a PriorityPicker.
460 note that the write-port wen, write-port data, and go_wr_i all need to
461 be on the exact same clock cycle. as there is a combinatorial loop bug
462 at the moment, these all use sync.
464 comb
, sync
= m
.d
.comb
, m
.d
.sync
467 # dictionary of lists of regfile write ports
468 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
470 # same for write ports.
471 # BLECH! complex code-duplication! BLECH!
473 for regfile
, spec
in byregfiles_wr
.items():
474 fuspecs
= byregfiles_wrspec
[regfile
]
475 wrpickers
[regfile
] = {}
477 if self
.regreduce_en
:
478 # argh, more port-merging
480 fuspecs
['o'] = [fuspecs
.pop('o')]
481 fuspecs
['o'].append(fuspecs
.pop('o1'))
482 if regfile
== 'FAST':
483 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
484 if 'fast2' in fuspecs
:
485 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
487 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
488 self
.connect_wrport(m
, fu_bitdict
, wrpickers
,
489 regfile
, regname
, fspec
)
491 def get_byregfiles(self
, readmode
):
493 mode
= "read" if readmode
else "write"
496 e
= self
.e
# decoded instruction to execute
498 # dictionary of lists of regfile ports
501 for (funame
, fu
) in fus
.items():
502 print("%s ports for %s" % (mode
, funame
))
503 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
505 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
507 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
508 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
510 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
513 rdflag
, read
= None, None
514 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
515 if regfile
not in byregfiles
:
516 byregfiles
[regfile
] = {}
517 byregfiles_spec
[regfile
] = {}
518 if regname
not in byregfiles_spec
[regfile
]:
519 byregfiles_spec
[regfile
][regname
] = \
520 (rdflag
, read
, write
, wid
, [])
521 # here we start to create "lanes"
522 if idx
not in byregfiles
[regfile
]:
523 byregfiles
[regfile
][idx
] = []
524 fuspec
= (funame
, fu
, idx
)
525 byregfiles
[regfile
][idx
].append(fuspec
)
526 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
528 # ok just print that out, for convenience
529 for regfile
, spec
in byregfiles
.items():
530 print("regfile %s ports:" % mode
, regfile
)
531 fuspecs
= byregfiles_spec
[regfile
]
532 for regname
, fspec
in fuspecs
.items():
533 [rdflag
, read
, write
, wid
, fuspec
] = fspec
534 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
535 print(" %s" % regname
, wid
, read
, write
, rdflag
)
536 for (funame
, fu
, idx
) in fuspec
:
537 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
538 print(" ", funame
, fu
, idx
, fusig
)
541 return byregfiles
, byregfiles_spec
544 yield from self
.fus
.ports()
545 yield from self
.e
.ports()
546 yield from self
.l0
.ports()
553 if __name__
== '__main__':
554 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
559 dut
= NonProductionCore(pspec
)
560 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
561 with
open("test_core.il", "w") as f
: