- self.valid = Signal(reset_less=True)
- self.insn_type = Signal(InternalOp, reset_less=True)
- self.nia = Signal(64, reset_less=True)
- self.write_reg = Data(5, name="rego")
- self.read_reg1 = Data(5, name="reg1")
- self.read_reg2 = Data(5, name="reg2")
- self.read_reg3 = Data(5, name="reg3")
- self.imm_data = Data(64, name="imm")
- self.write_spr = Data(10, name="spro")
- self.read_spr1 = Data(10, name="spr1")
- self.read_spr2 = Data(10, name="spr2")
- self.cr_sel = Data(3, name="cr_sel")
- #self.read_data1 = Signal(64, reset_less=True)
- #self.read_data2 = Signal(64, reset_less=True)
- #self.read_data3 = Signal(64, reset_less=True)
- #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
- #self.xerc = XerBits() # NO: this is from the XER SPR
- self.lk = Signal(reset_less=True)
- self.rc = Data(1, "rc")
- self.oe = Data(1, "oe")
- self.invert_a = Signal(reset_less=True)
- self.invert_out = Signal(reset_less=True)
- self.input_carry = Signal(CryIn, reset_less=True)
- self.output_carry = Signal(reset_less=True)
- self.input_cr = Signal(reset_less=True)
- self.output_cr = Signal(reset_less=True)
- self.is_32bit = Signal(reset_less=True)
- self.is_signed = Signal(reset_less=True)
- self.insn = Signal(32, reset_less=True)
- self.data_len = Signal(4, reset_less=True) # bytes
- self.byte_reverse = Signal(reset_less=True)
- self.sign_extend = Signal(reset_less=True)# do we need this?
- self.update = Signal(reset_less=True) # is this an update instruction?
+
+class DecodeCROut(Elaboratable):
+ """Decodes input CR from instruction
+
+ CR indices - insn fields - (not the data *in* the CR) require only 3
+ bits because they refer to CR0-CR7
+ """
+
+ def __init__(self, dec):
+ self.dec = dec
+ self.rc_in = Signal(reset_less=True)
+ self.sel_in = Signal(CROutSel, reset_less=True)
+ self.insn_in = Signal(32, reset_less=True)
+ self.cr_bitfield = Data(3, "cr_bitfield")
+ self.whole_reg = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+
+ comb += self.cr_bitfield.ok.eq(0)
+ comb += self.whole_reg.eq(0)
+ with m.Switch(self.sel_in):
+ with m.Case(CROutSel.NONE):
+ pass # No bitfield activated
+ with m.Case(CROutSel.CR0):
+ comb += self.cr_bitfield.data.eq(0)
+ comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
+ with m.Case(CROutSel.BF):
+ comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
+ comb += self.cr_bitfield.ok.eq(1)
+ with m.Case(CROutSel.BT):
+ comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
+ comb += self.cr_bitfield.ok.eq(1)
+ with m.Case(CROutSel.WHOLE_REG):
+ comb += self.whole_reg.eq(1)
+
+ return m
+
+
+class XerBits:
+ def __init__(self):
+ self.ca = Signal(2, reset_less=True)
+ self.ov = Signal(2, reset_less=True)
+ self.so = Signal(reset_less=True)