fix setting of SVSTATE.VL and MVL

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index aeecc897a3ae4168187691e0f2cfc619dfc81ed2..e9afcf21f1202bf3fecd57a9a175a34e9771be6a 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -368,6 +368,7 @@ def get_pdecode_idx_out(dec2, name):
     elif name == 'RT':
         if out_sel == OutSel.RT.value:
             return out, o_isvec
+    print ("get_pdecode_idx_out not found", name)
     return None, False
 
 
@@ -424,7 +425,9 @@ class ISACaller:
 
         # set up registers, instruction memory, data memory, PC, SPRs, MSR
         self.svp64rm = SVP64RM()
-        self.svstate = SVP64State(initial_svstate)
+        if isinstance(initial_svstate, int):
+            initial_svstate = SVP64State(initial_svstate)
+        self.svstate = initial_svstate
         self.gpr = GPR(decoder2, self, self.svstate, regfile)
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
@@ -694,6 +697,8 @@ class ISACaller:
 
         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
+        print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
+        print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
         sv_rm = pfx.rm.asint()
         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
@@ -860,8 +865,10 @@ class ISACaller:
             # (mapping name RA RB RC RS to in1, in2, in3)
             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
             if regnum is None:
+                # doing this is not part of svp64, it's because output
+                # registers, to be modified, need to be in the namespace.
                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
-            #regnum = yield getattr(self.decoder, name)
+            # in case getting the register number is needed, _RA, _RB
             regname = "_" + name
             self.namespace[regname] = regnum
             print('reading reg %s %d' % (name, regnum), is_vec)
@@ -953,8 +960,13 @@ class ISACaller:
                     if name == 'MSR':
                         print('msr written', hex(self.msr.value))
                 else:
-                    regnum = yield getattr(self.decoder, name)
-                    print('writing reg %d %s' % (regnum, str(output)))
+                    regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
+                                                name)
+                    if regnum is None:
+                        # temporary hack for not having 2nd output
+                        regnum = yield getattr(self.decoder, name)
+                        is_vec = False
+                    print('writing reg %d %s' % (regnum, str(output)), is_vec)
                     if output.bits > 64:
                         output = SelectableInt(output.value, 64)
                     self.gpr[regnum] = output