noticed the regular pattern in all pipe_data.py (regspecs).

[soc.git] / src / soc / fu / shift_rot / pipe_data.py

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 29f07efc4ac2b7f5164821db7de6d3e42fe8c130..16f0655435a75eab03fbe5dfb543a143b51ad8fc 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,49 +1,23 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.shift_rot.sr_input_record import CompSROpSubset
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from soc.fu.alu.pipe_data import ALUOutputData
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.logical.pipe_data import LogicalOutputData
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 
 
 class ShiftRotInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rs', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ca', '34,45')]
+    regspec = [('INT', 'ra', '0:63'),      # RA
+               ('INT', 'rb', '0:63'),      # RB
+               ('INT', 'rc', '0:63'),      # RS
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rs = Signal(64, reset_less=True) # RS
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.rs = self.ra, self.rc
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rs
-        yield self.rb
-        yield self.xer_ca
-        yield self.xer_so
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_so.eq(i.xer_so)]
-
-
-# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
-class ShiftRotPipeSpec:
-    regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
-    def __init__(self, id_wid, op_wid):
-        self.id_wid = id_wid
-        self.op_wid = op_wid
-        self.opkls = lambda _: self.opsubsetkls(name="op")
-        self.stage = None
-        self.pipekls = SimpleHandshakeRedir
+class ShiftRotPipeSpec(CommonPipeSpec):
+    regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
+    opsubsetkls = CompSROpSubset