-Subproject commit 6a79599c792e9271203c29082ee512a46930be85
+Subproject commit 041f868b620685068f375bce39c3aacf6aa986c4
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
class ALUPipeSpec(CommonPipeSpec):
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO
class ALUBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = ALUStages(pspec)
self._eqs = self.connect([self.pipe1])
op_bctarl CR, TAR, CTR
"""
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompBROpSubset
+ def rdflags(self, e): # in order of regspec
+ cr1_en = e.read_cr1.ok # CR A
+ spr1_ok = e.read_spr1.ok # SPR1
+ spr2_ok = e.read_spr2.ok # SPR2
+ return Cat(spr1_ok, spr2_ok, cr1_en, 1) # CIA CR SPR1 SPR2
class BranchBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = BranchStages(pspec)
self._eqs = self.connect([self.pipe1])
"""
+from nmigen import Cat
from nmigen.cli import rtlil
from soc.experiment.compalu_multi import MultiCompUnit
note that it is through MultiCompUnit.get_in/out that we *actually*
connect up the association between regspec variable names (defined
in the pipe_data).
+
+ note that the rdflags function obtains (dynamically, from instruction
+ decoding) which read-register ports are to be requested. this is not
+ ideal (it could be a lot neater) but works for now.
"""
def __init__(self, speckls, pipekls):
pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance)
alu = pipekls(pspec) # create actual NNNBasePipe
super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
+ def rdflags(self, e):
+ print (dir(self.alu))
+ return self.alu.pspec.rdflags(e)
+
##############################################################
# TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
+
#####################################################################
###### actual Function Units: these are "multi" stage pipelines #####
res[i] = inp[wrop]
return res
-def get_cu_rd_mask(n_src, inp):
- mask = 0
- for i in range(n_src):
- if i in inp:
- mask |= (1<<i)
- return mask
-
class TestRunner(FHDLTestCase):
def __init__(self, test_data, fukls, iodef, funit):
inp = get_inp_indexed(cu, iname)
# reset read-operand mask
- rdmask = get_cu_rd_mask(cu.n_src, inp)
+ rdmask = cu.rdflags(pdecode2.e)
yield cu.rdmaskn.eq(~rdmask)
# reset write-operand mask
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
opsubsetkls = CompCROpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA/RC
+ reg2_ok = e.read_reg2.ok # RB
+ full_reg = e.read_cr_whole # full CR
+ cr1_en = e.read_cr1.ok # CR A
+ cr2_en = e.read_cr2.ok # CR B
+ cr3_en = e.read_cr3.ok # CR C
+ return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)
class CRBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = CRStages(pspec)
self._eqs = self.connect([self.pipe1])
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
from soc.decoder.power_decoder2 import Data
class LogicalPipeSpec(CommonPipeSpec):
regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompLogicalOpSubset
+ def rdflags(self, e): # in order of regspec
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ return Cat(reg1_ok, reg2_ok) # RA RB
class LogicalBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = LogicalStages(pspec)
self._eqs = self.connect([self.pipe1])
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = MulStages1(pspec)
self.pipe2 = MulStages2(pspec)
self._eqs = self.connect([self.pipe1, self.pipe2])
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
from ieee754.fpcommon.getop import FPPipeContext
class ShiftRotPipeSpec(CommonPipeSpec):
regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
opsubsetkls = CompSROpSubset
+ def rdflags(self, e): # in order of regspec input
+ reg1_ok = e.read_reg1.ok # RA
+ reg2_ok = e.read_reg2.ok # RB
+ reg3_ok = e.read_reg3.ok # RS
+ return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA
class ShiftRotBasePipe(ControlBase):
def __init__(self, pspec):
ControlBase.__init__(self)
+ self.pspec = pspec
self.pipe1 = ShiftRotStages(pspec)
self._eqs = self.connect([self.pipe1])
projects / soc.git / commitdiff