git.libre-soc.org Git - soclayout.git/history - experiments10

2021-06-05	Luke Kenneth Casso...	add dummy pll to experiments10_verilog	blob \| commitdiff \| raw
2021-04-19	Luke Kenneth Casso...	code-comments	blob \| commitdiff \| raw \| diff to current
2021-04-19	Luke Kenneth Casso...	add two SRAMs, document how to do more	blob \| commitdiff \| raw \| diff to current
2021-04-14	Luke Kenneth Casso...	add an SRAM and wishbone to add test (makes it bigger)	blob \| commitdiff \| raw \| diff to current
2021-04-14	Luke Kenneth Casso...	connect up boundary scan to inputs/outputs	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	rename sys_clk in adder test experiments10_verilog...	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	rename JTAG port in adder test experiments10_verilog...	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	back to "working" verilog add	blob \| commitdiff \| raw \| diff to current
2021-04-09	Luke Kenneth Casso...	rename design of experiments10 to match ls180 chip...	blob \| commitdiff \| raw \| diff to current
2021-04-02	Luke Kenneth Casso...	experiment with nmigen verilog generation	blob \| commitdiff \| raw \| diff to current