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add dummy pll to experiments10_verilog
[soclayout.git]
/
experiments10_verilog
/
doDesign.py
2021-06-05
Luke Kenneth Casso...
add dummy pll to experiments10_verilog
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2021-06-05
Luke Kenneth Casso...
set various clocks to use H-Tree
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2021-04-14
Luke Kenneth Casso...
add an SRAM and wishbone to add test (makes it bigger)
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2021-04-12
Luke Kenneth Casso...
include (but do not use) FreePDK45 in experiments10
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2021-04-12
Luke Kenneth Casso...
rename sys_clk in adder test experiments10_verilog...
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2021-04-12
Luke Kenneth Casso...
rename JTAG port in adder test experiments10_verilog...
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2021-04-12
Luke Kenneth Casso...
back to "working" verilog add
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2021-04-09
Luke Kenneth Casso...
sigh, broken experiment10_verilog
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2021-04-09
Luke Kenneth Casso...
pad name starts with p_
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2021-04-09
Luke Kenneth Casso...
rename design of experiments10 to match ls180 chip...
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2021-04-02
Luke Kenneth Casso...
experiment with nmigen verilog generation
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