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rename sys_clk in adder test experiments10_verilog (success compile)
[soclayout.git] / experiments10_verilog /
2021-04-12 Luke Kenneth Casso... rename sys_clk in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... rename JTAG port in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... back to "working" verilog add tree | commitdiff
2021-04-09 Luke Kenneth Casso... sigh, broken experiment10_verilog tree | commitdiff
2021-04-09 Luke Kenneth Casso... whitespace cleanup tree | commitdiff
2021-04-09 Luke Kenneth Casso... pad name starts with p_ tree | commitdiff
2021-04-09 Luke Kenneth Casso... rename design of experiments10 to match ls180 chip... tree | commitdiff
2021-04-02 Luke Kenneth Casso... experiment with nmigen verilog generation tree | commitdiff