more work on orangecrab dram
[ls2.git] / src / ls2.py
2022-08-03 Tobias Platenmore work on orangecrab dram
2022-07-20 Tobias Platenmerge part 2 of Cesar's patch
2022-07-06 Tobias Platenfixed KeyError for rcs_arctic_tern_bmc_card
2022-06-30 Tobias Platenset dram_clk_freq to None
2022-05-17 Tobias Platenorangecrab: don't use async. set to 50 mhz.
2022-05-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-05-15 Tobias Platenset dram_clk_freq = 100.0e6 for orangecrab
2022-05-04 Luke Kenneth Casso... pass in freq setting to nextpnr-xilinx
2022-05-04 Luke Kenneth Casso... add micron n25q 128mb QSPI device to table of
2022-05-04 Luke Kenneth Casso... add tercel speed-up but missing id for arty a7 at the...
2022-05-03 Tobias Platenbegin dram support for ls2
2022-05-02 Tobias Platenadd spi for orangecrab
2022-04-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-04-30 Tobias Platenchange frequency for orangecrab, correct uart output
2022-04-30 Luke Kenneth Casso... nope, 24 mhz works, 27 does not
2022-04-30 Luke Kenneth Casso... update arty a7 clock frequency to 27 mhz, works with...
2022-04-24 Luke Kenneth Casso... doh
2022-04-24 Luke Kenneth Casso... list of hyperrams not just one
2022-04-22 Luke Kenneth Casso... move hyperram to 0x0000_00000 and 0x2000_0000
2022-04-22 Luke Kenneth Casso... add second hyperram module, for arty-a7,
2022-04-16 Luke Kenneth Casso... put versa_ecp5 back to synchronous at 50 mhz to test...
2022-04-16 Luke Kenneth Casso... remove stall from WBASyncBridges on master side
2022-04-16 Luke Kenneth Casso... attempting to get VERSA_ECP5 and Icarus Sim to work...
2022-04-16 Luke Kenneth Casso... add in extra delay-for-core in ECP5CRG
2022-04-16 Tobias Platenorangecrab: set clock frequency, remove ignored iostandard
2022-04-15 Luke Kenneth Casso... comment about UARTResource for orangecrab
2022-04-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-04-15 Tobias Platenadd orangecrab uart and toolchain
2022-04-15 Luke Kenneth Casso... checking simulation of Async DDR3
2022-04-15 Luke Kenneth Casso... work-in-progress
2022-04-15 Tobias Platenwhitespace
2022-04-15 Tobias Platenadd orangecrab to list of supported boards
2022-04-14 Luke Kenneth Casso... reduce versa_ecp5 clock freq to 50 mhz, reduce bit...
2022-04-14 Luke Kenneth Casso... add default args in DDR3SoC
2022-04-14 Luke Kenneth Casso... put fw_addr back to 0xff00_0000, xics.bin test passed
2022-04-14 Luke Kenneth Casso... move firmware to address 0x0 to test microwatt xics.bin
2022-04-14 Luke Kenneth Casso... bleh. add XICS_ICS and XICS_ICP but the patch is
2022-04-14 Luke Kenneth Casso... code-comments for when ASyncBridge is deployed
2022-04-14 Luke Kenneth Casso... add new dram_clk_freq argument which does nothing for now
2022-04-14 Luke Kenneth Casso... add a dramsync2x domain as well
2022-04-13 Luke Kenneth Casso... get microwatt-verilator sim running at different boot...
2022-04-12 Luke Kenneth Casso... add comments on locations where async bridge needs...
2022-04-11 Luke Kenneth Casso... too big, shift down to 2MB offset
2022-04-11 Luke Kenneth Casso... fix coldboot to boot from return address
2022-04-11 Luke Kenneth Casso... put versa_ecp5 below 50 mhz as a bodge-way to stop...
2022-04-10 Luke Kenneth Casso... Revert "Wire up missing CRG / DDR3 clock control /...
2022-04-09 Luke Kenneth Casso... add QSPI dump back in (smaller one) to check it is...
2022-04-09 Raptor Engineering... Wire up missing CRG / DDR3 clock control / reset signals
2022-04-09 Luke Kenneth Casso... shuffle addresses around a bit
2022-04-08 Luke Kenneth Casso... add DRAM offset into SYSCON and jump to DRAM if flash...
2022-04-08 Luke Kenneth Casso... add ELF reading to coldboot.c, move spi address to...
2022-04-08 Luke Kenneth Casso... add read of SYSCON and entry for SPIFlash
2022-04-08 Luke Kenneth Casso... up the delay-time on ddr3 reset, put loop around dram...
2022-04-08 Luke Kenneth Casso... comment/80-char limit
2022-04-07 Raptor Engineering... Enable DDR3 using a 50MHz clock on Versa 85
2022-04-07 Raptor Engineering... Move simulation HyperRAM pins off of DDR3 pins
2022-04-06 Luke Kenneth Casso... add QSPI support to arty_a7
2022-04-04 Luke Kenneth Casso... allow setting individual directions on QSPI dq0-dq3
2022-04-04 Luke Kenneth Casso... increase power-on-delay for icarus sim to allow reset...
2022-04-04 Luke Kenneth Casso... disable ethmac for now, pass firmware.hex to cypress...
2022-04-04 Luke Kenneth Casso... redo start address of firmware so it can be specified...
2022-04-02 Raptor Engineering... Add 10/100 MAC pins for Versa boards and enable MAC
2022-03-31 Luke Kenneth Casso... got icarus verilog model of QSPI working and it returns...
2022-03-31 Luke Kenneth Casso... whitespace cleanup
2022-03-31 Raptor Engineering... Fix Tercel QSPI master connections
2022-03-31 Luke Kenneth Casso... remove {err} feature from Tercel
2022-03-29 Luke Kenneth Casso... add err wishbone feature to Tercel
2022-03-29 Luke Kenneth Casso... remove clk from spi_flash,
2022-03-29 Luke Kenneth Casso... add qspi module to arty_a7
2022-03-29 Luke Kenneth Casso... use nmigen_boards naming conventions for SPIFlash
2022-03-29 Luke Kenneth Casso... update comments, link/setup of peripherals
2022-03-29 Luke Kenneth Casso... add TODO comments about using platform.add_resources
2022-03-29 Luke Kenneth Casso... whitespace cleanup, 80 char limit
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC
2022-03-28 Raptor Engineering... Fix instructions in comment
2022-03-27 Luke Kenneth Casso... set reset from ResetSignal not straight to 1 for HyperRAM
2022-03-27 Luke Kenneth Casso... try latency of 7 for winbond hyperram
2022-03-27 Luke Kenneth Casso... set upper CSns on HyperRAM to zero and set reset_n HI
2022-03-26 Luke Kenneth Casso... add all 4 CSn lines for Quad HyperRAM PMOD
2022-03-26 Luke Kenneth Casso... grr
2022-03-26 Luke Kenneth Casso... reduce power-on-delay bits to 2 for icarus sim ecp5
2022-03-26 Luke Kenneth Casso... sort out platform IO pads for iverilog hyperram sim
2022-03-25 Luke Kenneth Casso... rename ECP5 CRG, move source, remove duplicate version
2022-03-25 Luke Kenneth Casso... up arty a7 frequency to 40 mhz
2022-03-24 Luke Kenneth Casso... increase delay on ECP5 ulx3s
2022-03-24 Luke Kenneth Casso... check ulx3s, add CRG support for ulx3s
2022-03-24 Luke Kenneth Casso... establish power-on reset stabilisation for Arty A7...
2022-03-22 Luke Kenneth Casso... add hack to modify VERSA_ECP5 85F platform to speed...
2022-03-22 Luke Kenneth Casso... adding hyperram for arty a7 and also adding a workaroun...
2022-03-20 Luke Kenneth Casso... crank A7 FPGA speed down to experiment
2022-03-20 Luke Kenneth Casso... first cut at Arty A7 Clock-Reset-Generator with S7 PLL
2022-03-19 Luke Kenneth Casso... add VERSA_ECP5 85F custom board
2022-03-19 Luke Kenneth Casso... set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
2022-03-19 Luke Kenneth Casso... correct pin names for HyperRAMResource, indent spi0...
2022-03-19 Luke Kenneth Casso... fixed hyperram pin names which was stopping verilator...
2022-03-19 Luke Kenneth Casso... disable hyperram for now (under investigation)
2022-03-19 Luke Kenneth Casso... adding in hyperram peripheral
2022-03-18 Luke Kenneth Casso... whitespace / module-import / comments / tidyup
2022-03-18 Luke Kenneth Casso... beginning to add hyperram module
2022-03-18 Luke Kenneth Casso... whitespace cleanup and make SPI core (temporarily)...
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