SVP64RMModeDecode detects Post-Inc LDST-imm mode
[openpower-isa.git] / src / openpower / decoder / isa /
2022-10-14 Luke Kenneth Casso... SVP64RMModeDecode detects Post-Inc LDST-imm mode
2022-10-14 Luke Kenneth Casso... correct comments
2022-10-14 Luke Kenneth Casso... add in zeroing on test strncpy
2022-10-14 Luke Kenneth Casso... remove unneeded svstate from test
2022-10-14 Luke Kenneth Casso... add strncpy example - 6 instructions
2022-10-14 Luke Kenneth Casso... add sv.stwu/pi example in test_sv_load_store_postinc
2022-10-14 Luke Kenneth Casso... add ld/st-immediate "post-inc" mode support. unit test...
2022-10-11 Luke Kenneth Casso... add asciidump option to Mem class
2022-10-11 Luke Kenneth Casso... whoops zero-error on masked-out
2022-10-10 Luke Kenneth Casso... add elwidth overrides on Indexed REMAP, 8-bit example...
2022-10-10 Luke Kenneth Casso... add elwidth overrides to get_idx_out2
2022-10-08 Luke Kenneth Casso... fix format in debug log
2022-10-08 Luke Kenneth Casso... forgot to add offset on GPR() get
2022-10-08 Luke Kenneth Casso... add elwidth overrides on destination (write) in ISACaller.
2022-10-08 Luke Kenneth Casso... split out base,offset in register decoding for elwidth...
2022-10-08 Luke Kenneth Casso... add 8-bit elwidth alu svp64 case
2022-10-07 Luke Kenneth Casso... more work on inssort. add useful reg-dump in ISACaller
2022-10-06 Luke Kenneth Casso... nope. failfirst needs to always save the result, but...
2022-10-06 Luke Kenneth Casso... fix fail-first to exclude failed element in VLi=0 mode
2022-10-06 Luke Kenneth Casso... sort out CROPs fail-first in ISACaller. needed to...
2022-10-06 Luke Kenneth Casso... make fail-first cope with sv.cmp which uses CR[BF]
2022-10-06 Luke Kenneth Casso... add insert sort svp64 test
2022-10-06 Luke Kenneth Casso... search for BF in registers to over-ride Vector lookup...
2022-10-06 Luke Kenneth Casso... starting to add sv.cmp support and failfirst, had to add
2022-10-02 Luke Kenneth Casso... comments for why preinc is called for svstep
2022-10-01 Luke Kenneth Casso... skip svstate_pre_inc on svremap
2022-10-01 Luke Kenneth Casso... no svstate instruction
2022-10-01 Luke Kenneth Casso... svstep calls SVSTATE_NEXT so needs svstate_pre_inc
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... minor cleanup in ISACaller on result handling
2022-10-01 Luke Kenneth Casso... simplify ISACaller execute_one
2022-10-01 Luke Kenneth Casso... simplify setting default SVSHAPE SPRs to zero
2022-09-30 Luke Kenneth Casso... ctr mode not needed, just use unconditional CTR dec
2022-09-30 Luke Kenneth Casso... set srcstep/dststep to zero in StepLoop (ISACaller...
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... comments/variables-cleanup
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... add sv.bc/vs - VLset - test. truncates VL at the vector...
2022-09-30 Luke Kenneth Casso... add new sv.bc CTR-loop test, subtracts VL from CTR
2022-09-30 Luke Kenneth Casso... whitespace
2022-09-30 Luke Kenneth Casso... use regs variables in get_predint
2022-09-30 Luke Kenneth Casso... comments
2022-09-30 Jacob Lifshayallow logging function to be overridden for Mem.log_fancy
2022-09-29 Jacob Lifshayconvert svp64 bigint unittests to use TestAccumulatorBase
2022-09-29 Jacob Lifshayfinish changing to use adde, not addeo for bigint add
2022-09-29 Luke Kenneth Casso... sv.adde not sv.addeo
2022-09-29 Luke Kenneth Casso... add carry-roll-over-vector-mul-with-add (!) unit test
2022-09-29 Luke Kenneth Casso... comments
2022-09-29 Luke Kenneth Casso... add shift-left and shift-right scalar-to-vector tests
2022-09-29 Luke Kenneth Casso... update iterators in ISACaller, not used yet
2022-09-29 Jacob Lifshayrename madded->maddedu for consistency with PowerISA...
2022-09-29 Jacob Lifshayrename divrem2du->divmod2du for consistency with PowerI...
2022-09-29 Jacob Lifshayadd bigint tests and fix madded pseudocode
2022-09-29 Jacob Lifshayadd bigint ops
2022-09-29 Jacob Lifshayremove unnecesary commented code
2022-09-28 Luke Kenneth Casso... srcstep
2022-09-28 Luke Kenneth Casso... rename iterators init function
2022-09-28 Luke Kenneth Casso... redundant comment
2022-09-28 Luke Kenneth Casso... split out svstate update in ISACaller
2022-09-28 Luke Kenneth Casso... move failfirst check to separate function in ISACaller
2022-09-28 Luke Kenneth Casso... bugfix reset remaps and get subvl early
2022-09-28 Luke Kenneth Casso... comments on horizontal-or
2022-09-28 Luke Kenneth Casso... make matrix horizontal-remap example more generic
2022-09-28 Luke Kenneth Casso... add horizontal-or-reduction example that thoroughly...
2022-09-27 Luke Kenneth Casso... add unpack predicated unit test
2022-09-27 Luke Kenneth Casso... hack to check skipping on predicate being all-zero.
2022-09-27 Luke Kenneth Casso... sort out predicate loop-skip on pack/unpack
2022-09-27 Luke Kenneth Casso... adapt loops to include predicate-mask skipping in ISACaller
2022-09-26 Luke Kenneth Casso... skipping on maskedout elements de-restricted when subst...
2022-09-26 Luke Kenneth Casso... add first predicate-mask test of pack/unpack
2022-09-26 Luke Kenneth Casso... get pack/unpack tests to use sv.ori to copy sequence...
2022-09-26 Luke Kenneth Casso... finally got pack/unpack working
2022-09-26 Luke Kenneth Casso... code-morph on loop-end detection in ISACaller
2022-09-26 Luke Kenneth Casso... explicit test of src/dststep end-condition in ISACaller...
2022-09-25 Konstantinos Marga... comment out debug dumps
2022-09-24 Luke Kenneth Casso... add extra RC1 test, without VLI.
2022-09-24 Luke Kenneth Casso... add RC1 support to ISACaller.
2022-09-23 Luke Kenneth Casso... check svstate (vl) in failfirst test
2022-09-23 Luke Kenneth Casso... add data-dependent fail-first mode, Rc=1 variant not...
2022-09-23 Luke Kenneth Casso... remove need for explicit-hack for "pcdec." - rc column...
2022-09-23 Luke Kenneth Casso... lots of really bad hacks, here
2022-09-23 Luke Kenneth Casso... fix/hack some bugs in prefix_codes_cases
2022-09-23 Luke Kenneth Casso... add (sigh) to the hack-job get_pdecode_idx_out2() in...
2022-09-23 Luke Kenneth Casso... change variablename dec2.use_svp64_fft to implicit_rs
2022-09-23 Luke Kenneth Casso... rename all "fft" variables in PowerDecoder2 because...
2022-09-23 Jacob Lifshayadd pcdec -- doesn't yet work due to broken ISACaller...
2022-09-23 Jacob Lifshayfix 'write reg ' log call
2022-09-23 Jacob Lifshayadd RC input to isa/caller.py
2022-09-23 Jacob Lifshayformat code
2022-09-22 Luke Kenneth Casso... add first (correctly-working) ctr-mode sv.bc test
2022-09-22 Konstantinos Marga... dump memory
2022-09-21 Luke Kenneth Casso... add series of double-stride options to test_caller_svp6...
2022-09-21 Luke Kenneth Casso... do not set striding on costables, keep them contiguous.
2022-09-21 Luke Kenneth Casso... scale-up svshape pseudo-code for striding in DCT/FFT
2022-09-21 Luke Kenneth Casso... fix dct/fft test-functions with new "scaling" parameter
2022-09-21 Luke Kenneth Casso... whoops stride already has +1 from SVSTATE class
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