add elwidth overrides to get_idx_out2
[openpower-isa.git] / src / openpower / sv /
2022-10-08 Luke Kenneth Casso... add rfscv to major_19.csv, add test_pysvp64dis.py unit...
2022-10-08 Luke Kenneth Casso... drat
2022-10-08 Luke Kenneth Casso... add sc and scv support after moving from major.csv...
2022-10-08 Luke Kenneth Casso... vector name "RSp" not recognised in sv.stq, added as...
2022-10-08 Luke Kenneth Casso... add stq to CSV files and unit test to test_pysvp64dis.py
2022-10-08 Luke Kenneth Casso... convert TargetAddrOperand to base class EXTSOperand
2022-10-08 Luke Kenneth Casso... add lq and CONST_DQ
2022-10-08 Luke Kenneth Casso... restore tests, accidentally disabled
2022-10-08 Luke Kenneth Casso... add addex to csv and sv_analysis db. also needs CryIn...
2022-10-06 Luke Kenneth Casso... add PredicateBaseRM decode to CR Ops Simple mode as...
2022-10-06 Luke Kenneth Casso... add vli mode to ff=5 CR ops
2022-10-06 Luke Kenneth Casso... add sv.cmp (ffirst-5) decode/encode asm support
2022-10-06 Luke Kenneth Casso... slightly different crops failfirst mode bits
2022-10-06 Luke Kenneth Casso... add sv.cmp and try fail-first test_pysvp64dist.py
2022-09-30 Jacob Lifshayfix pcdec. assembly -- merge into va_form() since it...
2022-09-30 Jacob Lifshayrewrite pcdec. pseudocode to work better for JPEG
2022-09-29 Jacob Lifshayrename madded->maddedu for consistency with PowerISA...
2022-09-29 Jacob Lifshayrename divrem2du->divmod2du for consistency with PowerI...
2022-09-29 Jacob Lifshayadd bigint ops
2022-09-29 Jacob Lifshayadd missing DRAFT comment
2022-09-25 Dmitry Selyutintest_pysvp64dis: sort ld/st idx stride specs
2022-09-25 Dmitry Selyutinpysvp64asm: fix VLi attribute access
2022-09-25 Luke Kenneth Casso... have to sanity-check dz/zz after full qualifier-process...
2022-09-25 Luke Kenneth Casso... add dz/sz assertion in is_bc mode
2022-09-25 Luke Kenneth Casso... whitespace
2022-09-24 Luke Kenneth Casso... move sea check to after all qualifiers are checked
2022-09-24 Luke Kenneth Casso... check variable rather than explicit == LDST_IDX
2022-09-24 Luke Kenneth Casso... add elstrided/sea on ldst_idx mode
2022-09-24 Dmitry Selyutintest_pysvp64dis: test ld/st idx SEA (simple)
2022-09-24 Dmitry Selyutinpysvp64asm: support /sea specifier
2022-09-24 Dmitry Selyutinpysvp64asm: fix comment layout
2022-09-24 Luke Kenneth Casso... set sv_mode to 0b01 in element-strided
2022-09-24 Luke Kenneth Casso... frickin frick
2022-09-24 Luke Kenneth Casso... add assert to stop failfirst+sea
2022-09-24 Luke Kenneth Casso... add extra test_pysvp64dis.py test for ff=~RC1/vli mode
2022-09-24 Luke Kenneth Casso... comment inv,CRbit swap in decode_bo
2022-09-24 Dmitry Selyutinsv_binutils: support RS opindex
2022-09-24 Dmitry Selyutinsv_binutils: provide Boolean class and Rc field
2022-09-24 Dmitry Selyutinpower_insn: replace Record.function with Record.mode
2022-09-24 Dmitry Selyutinpysvp64asm: expand vector register macros
2022-09-24 Dmitry Selyutinsv_binutils: support opcodes offset representation
2022-09-24 Dmitry Selyutinsv_binutils: fix fields traversal
2022-09-24 Dmitry Selyutinsv_binutils: generate svp64_cr_in2 opindices
2022-09-24 Dmitry Selyutinsv_binutils: generate BA opindex
2022-09-24 Dmitry Selyutinpower_fields: restore class-oriented traversal
2022-09-23 Luke Kenneth Casso... whoops consistent inversion of inv,CRbit was CRbit,inv
2022-09-23 Luke Kenneth Casso... extra failfirst dis tests
2022-09-23 Luke Kenneth Casso... remove barse-ackwardsness, use SelectableInt() in decode_bo
2022-09-23 Luke Kenneth Casso... put back the barse-ackward decode_bo inversion of ...
2022-09-23 Luke Kenneth Casso... lots of really bad hacks, here
2022-09-23 Jacob Lifshayadd pcdec -- doesn't yet work due to broken ISACaller...
2022-09-23 Jacob Lifshayformat code
2022-09-21 Luke Kenneth Casso... add sv.madd* to sv_analysis
2022-09-20 Luke Kenneth Casso... minor codemorph, whitespace
2022-09-20 Luke Kenneth Casso... sv.bc reclassified as RM-2P-1S by eliminating SPRs.
2022-09-20 Luke Kenneth Casso... remove messy string identification, use RM Mode from...
2022-09-20 Luke Kenneth Casso... add quick test and loooong test of pysvp64dis - branche...
2022-09-20 Dmitry Selyutinpysvp64asm: fix sz handling
2022-09-20 Dmitry Selyutintest_pysvp64dis: test vli specifier
2022-09-20 Dmitry Selyutinpysvp64asm: support vli specifier
2022-09-20 Luke Kenneth Casso... missed one sorting order in test_pysvp64dis.py
2022-09-20 Luke Kenneth Casso... sort specifiers in pysvp64dis in lexicographical order
2022-09-20 Luke Kenneth Casso... add two extra tests, sv.bc/m=r3/sz
2022-09-20 Dmitry Selyutinpysvp64asm: update sz upon snz specifier
2022-09-20 Luke Kenneth Casso... add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to...
2022-09-20 Dmitry Selyutinpower_insn: support vs/vsi/vsb/vsbi/ctr/cti specifiers
2022-09-20 Dmitry Selyutinpysvp64asm: support branch modes
2022-09-20 Dmitry Selyutinpower_insn: support common branch disassembly
2022-09-19 Dmitry Selyutinpower_insn: simplify branch table
2022-09-19 Luke Kenneth Casso... add bc_ctr and bc_cti but not used yet
2022-09-19 Dmitry Selyutintest_pysvp64dis: test els specifier
2022-09-18 Luke Kenneth Casso... fix predicate mask case when smask was zero but mmode...
2022-09-18 Dmitry Selyutinpysvp64asm: restore original BO
2022-09-18 Luke Kenneth Casso... reverse decode_bo inv/eq/lt/le/etc. thing
2022-09-18 Luke Kenneth Casso... dumb. accidentally removed test-call
2022-09-18 Luke Kenneth Casso... add unit tests for Rc=1 ffirst/predicate-result
2022-09-18 Dmitry Selyutintest_pysvp64dis: test RC1/~RC1 in ff/pr
2022-09-18 Dmitry Selyutinpysvp64asm: make zz also set src_zero
2022-09-18 Luke Kenneth Casso... adapt test_12_mr to /mrr and /mr modes, svm is gone...
2022-09-18 Dmitry Selyutintest_pysvp64dis: test mrr/svm specifiers
2022-09-18 Luke Kenneth Casso... remove subvector mode from sv/trans/svp64.py
2022-09-18 Luke Kenneth Casso... change sv/trans/svp64.py source/dest elwidth assembler...
2022-09-18 Dmitry Selyutintest_pysvp64dis: test sw specifier
2022-09-17 Luke Kenneth Casso... add sat/satu test_12_sat to test_pysvp64dis.py
2022-09-17 Dmitry Selyutinpysvp64asm: SVP64 instruction debug logs
2022-09-17 Luke Kenneth Casso... whoops. mode-bits need to be put in MSB0 order. sigh
2022-09-17 Luke Kenneth Casso... add zz mode to sv/trans/svp64.py as a hack
2022-09-17 Luke Kenneth Casso... remove sv.setvl/pk/up/pu - these are all gone in favour...
2022-09-17 Luke Kenneth Casso... add SVmask_src enum, rename fields to EN and NO to...
2022-09-17 Luke Kenneth Casso... as a double-check sv_analysis new CSV column "SM" was...
2022-09-17 Luke Kenneth Casso... add a "SM" column into RM*.csv (and LDSTRM*.csv) identi...
2022-09-17 Luke Kenneth Casso... add sv.add/ew=XX test to test_pysvp64dis.py
2022-09-17 Luke Kenneth Casso... add vec2/3/4 test_pysvp64dis test
2022-09-16 Luke Kenneth Casso... comments on test_9_fptrans
2022-09-16 Dmitry Selyutintest_pysvp64dis: test fptrans
2022-09-16 Dmitry Selyutinsv_binutils_fptrans: adopt script for reuse
2022-09-15 Dmitry Selyutinsv_binutils_fptrans: fix disassembly
2022-09-15 Dmitry Selyutinsv_binutils_fptrans: fptrans binutils generator
2022-09-15 Luke Kenneth Casso... add minor_4.csv for maddld/maddhdu/maddhd and to insn_d...
2022-09-14 Jacob Lifshayfix sv_analysis for fpown and frootn
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