Removed extraneous variable from 'ports=[..]' of main in bperm.py
[soc.git] / src / soc / alu / main_stage.py
2020-05-17 Luke Kenneth Casso... whitespace cleanup
2020-05-15 Michael NolanImplement OP_CMPEQB
2020-05-14 Luke Kenneth Casso... add comment about CMP swapping
2020-05-14 Luke Kenneth Casso... move inversion of cmp into output stage by inverting...
2020-05-14 Michael NolanImplement OP_CMP
2020-05-14 Luke Kenneth Casso... add TODO comments on Logical pipeline
2020-05-13 Luke Kenneth Casso... minor tidyup
2020-05-13 Luke Kenneth Casso... comments on ALU pipeline
2020-05-13 Luke Kenneth Casso... remove Logical operations from ALU pipeline
2020-05-13 Luke Kenneth Casso... comments (and whitespace
2020-05-13 Michael NolanAdd support for OP_EXTS
2020-05-12 Michael NolanRemove rotates and shifts from alu
2020-05-11 Michael NolanActually implement rlwimi
2020-05-10 Michael NolanImplement rlwimi as well
2020-05-10 Michael NolanImplement rlwinm in alu
2020-05-09 Luke Kenneth Casso... sigh ton of syntax errors
2020-05-09 Luke Kenneth Casso... bit of reorg, trick on add - put carry in into the LSB
2020-05-09 Michael NolanHandle algebraic shifts too
2020-05-09 Michael NolanImplement logical shift right
2020-05-09 Michael NolanAdd support for sld
2020-05-09 Michael NolanChange shift left to be implemented with rotate and...
2020-05-09 Michael NolanAdd shift left opcode to main_stage
2020-05-09 Luke Kenneth Casso... comment where ALUIntermediateData to go
2020-05-09 Luke Kenneth Casso... missing sticky-overflow pass-through from middle stage
2020-05-08 Michael NolanAdd comments about the purpose of each alu stage
2020-05-08 Michael NolanAdd and or and xor to main_stage
2020-05-08 Michael NolanAdd carry in and out
2020-05-08 Michael NolanAdd extra bits (carry, overflow, etc) to input and...
2020-05-08 Michael NolanBegin adding main ALU stage