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Removed extraneous variable from 'ports=[..]' of main in bperm.py
[soc.git]
/
src
/
soc
/
alu
/
main_stage.py
2020-05-17
Luke Kenneth Casso...
whitespace cleanup
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2020-05-15
Michael Nolan
Implement OP_CMPEQB
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2020-05-14
Luke Kenneth Casso...
add comment about CMP swapping
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2020-05-14
Luke Kenneth Casso...
move inversion of cmp into output stage by inverting...
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2020-05-14
Michael Nolan
Implement OP_CMP
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2020-05-14
Luke Kenneth Casso...
add TODO comments on Logical pipeline
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2020-05-13
Luke Kenneth Casso...
minor tidyup
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2020-05-13
Luke Kenneth Casso...
comments on ALU pipeline
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2020-05-13
Luke Kenneth Casso...
remove Logical operations from ALU pipeline
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2020-05-13
Luke Kenneth Casso...
comments (and whitespace
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2020-05-13
Michael Nolan
Add support for OP_EXTS
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2020-05-12
Michael Nolan
Remove rotates and shifts from alu
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2020-05-11
Michael Nolan
Actually implement rlwimi
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2020-05-10
Michael Nolan
Implement rlwimi as well
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2020-05-10
Michael Nolan
Implement rlwinm in alu
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2020-05-09
Luke Kenneth Casso...
sigh ton of syntax errors
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2020-05-09
Luke Kenneth Casso...
bit of reorg, trick on add - put carry in into the LSB
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2020-05-09
Michael Nolan
Handle algebraic shifts too
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2020-05-09
Michael Nolan
Implement logical shift right
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2020-05-09
Michael Nolan
Add support for sld
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2020-05-09
Michael Nolan
Change shift left to be implemented with rotate and...
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2020-05-09
Michael Nolan
Add shift left opcode to main_stage
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2020-05-09
Luke Kenneth Casso...
comment where ALUIntermediateData to go
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2020-05-09
Luke Kenneth Casso...
missing sticky-overflow pass-through from middle stage
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2020-05-08
Michael Nolan
Add comments about the purpose of each alu stage
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2020-05-08
Michael Nolan
Add and or and xor to main_stage
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2020-05-08
Michael Nolan
Add carry in and out
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2020-05-08
Michael Nolan
Add extra bits (carry, overflow, etc) to input and...
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2020-05-08
Michael Nolan
Begin adding main ALU stage
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