move DEC and TB from StateRegs to FastRegs for several reasons
[soc.git] / src / soc / decoder /
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth Casso... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-05 Luke Kenneth Casso... add stbcix and lwzcix to power_enum list
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-09-02 Luke Kenneth Casso... when mtocrf FXM is 0, the CR has to be set to CR7
2020-09-02 Luke Kenneth Casso... add bc ctr regression test when CTR=0 and CTR=1
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing...
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-29 Luke Kenneth Casso... slowly morphing towards using an XER bit-field selector...
2020-08-29 Luke Kenneth Casso... yep disable OE for MULH64/32 and EXTS and CNTZ
2020-08-29 Luke Kenneth Casso... investigating CR mtocrf / mfocrf
2020-08-29 Luke Kenneth Casso... allow pseudocode numbering to decrement in for-loops
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask.
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... really bad hack to fix simulator bug in carry handling
2020-08-27 Luke Kenneth Casso... incompatibility with POWER9 on mulhw/u due to lack...
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations
2020-08-27 Luke Kenneth Casso... need to read SO if Rc=1
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Luke Kenneth Casso... investigating div fsm and simulator bug
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Luke Kenneth Casso... update copyright notices to include additional primary...
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-17 Luke Kenneth Casso... turn SelectableInt less/greater into signed versions.
2020-08-14 Luke Kenneth Casso... bad hack to get HSRR0/1 to be "same" as SRR0/1
2020-08-14 Luke Kenneth Casso... bug in isa parser not recognising MSR as declared variable
2020-08-14 Luke Kenneth Casso... stop trying to read swap files
2020-08-14 Luke Kenneth Casso... update submodule, add hrfid
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... move regspec / rdflag decoding functions out of PowerDe...
2020-08-14 Luke Kenneth Casso... reduce decoder pathways when exception occurs
2020-08-13 Luke Kenneth Casso... sigh. convert Fast regfile to binary
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Luke Kenneth Casso... MULS on parameter b needed to check whether it was...
2020-08-04 Luke Kenneth Casso... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-04 Luke Kenneth Casso... whitespace after autopep8 messed up
2020-08-04 Luke Kenneth Casso... msr and pc moved to "state" in PowerDecode2
2020-08-03 Luke Kenneth Casso... pass state (MSR/PC) around between PowerDecode2, DMI...
2020-08-01 Luke Kenneth Casso... add quick test of litex bios IMM64 macro
2020-07-31 Luke Kenneth Casso... reorg DecodeB in power_decoder2.py to sign-extend immed...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-25 Luke Kenneth Casso... hilarious. only just caught a bug where overflow was...
2020-07-24 Luke Kenneth Casso... annoying, yet more typos
2020-07-24 Luke Kenneth Casso... annoying, typo
2020-07-24 Luke Kenneth Casso... better debug assert log message
2020-07-24 Luke Kenneth Casso... remove bad hack calling trunc_divs/trunc_mods
2020-07-24 Luke Kenneth Casso... restore modification to caller.py from reversion of...
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller"
2020-07-24 Luke Kenneth Casso... bug found in pseudocode reader when assembly code has...
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-22 Luke Kenneth Casso... set additional MSR bits according to v3.0B spec when...
2020-07-22 Luke Kenneth Casso... use (new) MSRb and PIb which has auto-bigendian numbers
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-21 Luke Kenneth Casso... convert branch pipeline to use msr/cia as immediates
2020-07-21 Luke Kenneth Casso... set ISACaller.msr rather than namespace[MSR]
2020-07-21 Luke Kenneth Casso... when running an exception (trap) after "reset" must...
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into...
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... comment explaining why not to call self.trap in PowerDe...
2020-07-17 Jacob Lifshayadd missing fixedldstcache.py to .gitignore
2020-07-16 Luke Kenneth Casso... sigh, bug in sprset.patch
2020-07-16 Luke Kenneth Casso... get trap compunit test working, adding bigendian and msr
2020-07-15 Luke Kenneth Casso... simplify instr_is_priv
2020-07-15 Luke Kenneth Casso... move traptype to soc.consts
2020-07-15 Luke Kenneth Casso... whoops forgot to update PC after trap in ISACaller
2020-07-15 Luke Kenneth Casso... move priv test to above illegal/trap test
2020-07-15 Luke Kenneth Casso... minor reorg on PowerDecoder2, use switch/case rather...
2020-07-15 Luke Kenneth Casso... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth Casso... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth Casso... use case statement in PowerDecode2
2020-07-15 Luke Kenneth Casso... select RA based on LDSTMode.update in PowerDecode2
2020-07-15 Luke Kenneth Casso... add cache cx to LDSTMode
2020-07-15 Luke Kenneth Casso... remove unused class XerBits
2020-07-14 Luke Kenneth Casso... attempting to access self.msr directly
2020-07-14 Luke Kenneth Casso... add priv instruction checking to ISACaller simulator
2020-07-14 Luke Kenneth Casso... add in privileged instruction decision-making in PowerD...
2020-07-14 Luke Kenneth Casso... comments on PowerDecode2
2020-07-14 Luke Kenneth Casso... add MSR to PowerDecoder2
2020-07-13 Luke Kenneth Casso... remove unneeded spec patching
2020-07-13 Luke Kenneth Casso... enable extswsli tests, fix spec-patching
2020-07-13 Luke Kenneth Casso... fix read of sliced register
2020-07-13 Luke Kenneth Casso... not perfect but close enough: add read registers RA...
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... modify PowerDecoder to read LDSTMode correctly
2020-07-12 Luke Kenneth Casso... change CSV LD/ST update field to LDSTMode (support...
2020-07-12 Luke Kenneth Casso... missed setting of link register on OP_BC in PowerDecoder2
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-11 Luke Kenneth Casso... whoops output trunc_divs not trunc_div
2020-07-11 Luke Kenneth Casso... special test for mul hw to cope with ignoring OE flag
2020-07-10 Luke Kenneth Casso... add a DIVS function as separate and discrete from floor_div
2020-07-10 Luke Kenneth Casso... check for div_overflow equal to None rather than == 1
2020-07-10 Jacob Lifshayswitch to using Signal.width instead of Signal.shape...
2020-07-10 Jacob Lifshayformat file
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