dcache: improve debug output
[soc.git] / src / soc / experiment / dcache.py
2021-07-14 Tobias Platendcache: improve debug output
2021-06-20 Tobias Platendcache: add debug output
2021-05-13 Luke Kenneth Casso... yet more debug log stuff for DCache, this time on Cache...
2021-05-13 Luke Kenneth Casso... ha, hilarious: swapped TLBUpdate output sizes db_out...
2021-05-13 Luke Kenneth Casso... whoops TLBIE must *clear* the valid bit not set it...
2021-05-13 Luke Kenneth Casso... more debug Display in dcache.py
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache...
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport
2021-05-02 Luke Kenneth Casso... add nc argument to dcache load/store tests
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-05-01 Luke Kenneth Casso... dcache store test: data goes in one cycle AFTER valid...
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test
2021-04-26 Luke Kenneth Casso... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth Casso... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth Casso... simplify dcache test
2021-04-25 Luke Kenneth Casso... spelling mistake
2021-04-25 Luke Kenneth Casso... remove RegStage1.real_adr temporary from dcache
2021-04-25 Luke Kenneth Casso... do not overwrite parameter ra in dcache
2021-04-25 Luke Kenneth Casso... comment out dcache_store from test, not the problem
2021-04-25 Luke Kenneth Casso... remove unneeded code
2021-04-25 Luke Kenneth Casso... read req in wb_in.stall, dcache
2021-04-25 Luke Kenneth Casso... add single regression test for dcache
2021-04-25 Luke Kenneth Casso... add TODO comment in dcache
2021-04-25 Luke Kenneth Casso... move Signals in dcache to relevant context
2021-04-25 Luke Kenneth Casso... dcache Elif used where If should have been
2021-04-25 Luke Kenneth Casso... whoops should be cyc & ~ack
2021-04-25 Luke Kenneth Casso... hard-code dcache stall signal to non-pipelined mode
2021-04-24 Luke Kenneth Casso... increase memory size in dcache test
2021-04-24 Luke Kenneth Casso... increase size of random dcache testing by 10
2021-04-24 Luke Kenneth Casso... fix errors in dcache unit test
2021-04-22 Luke Kenneth Casso... add debugging and buffering to CacheRam
2021-04-22 Luke Kenneth Casso... whitespace
2021-04-22 Luke Kenneth Casso... r1.end_row_ix off-by-one in dcache
2021-04-22 Luke Kenneth Casso... sync missing in dcache
2021-04-22 Luke Kenneth Casso... dcache.py code-comments
2021-04-22 Luke Kenneth Casso... cleanup dcache
2021-04-22 Luke Kenneth Casso... error using sync, should have been comb
2021-04-21 Luke Kenneth Casso... experimenting with dcache
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-10-05 Luke Kenneth Casso... add debug / investigation print statements
2020-10-01 Luke Kenneth Casso... arg CacheRam read output needs delay by 1 cycle
2020-10-01 Luke Kenneth Casso... do not pass cache row array around, just the current row
2020-09-14 Luke Kenneth Casso... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth Casso... add array signal names
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... TLB PLRUs are of TLB_WAY_BITS width
2020-09-14 Luke Kenneth Casso... fix mmu perms/lookup in dcache
2020-09-13 Luke Kenneth Casso... dcache truncate wishbone address, store real_addr in...
2020-09-13 Luke Kenneth Casso... MMU test
2020-09-13 Luke Kenneth Casso... sort out ariane PLRU, rename/clarify
2020-09-13 Luke Kenneth Casso... rename cache_valid_bits to cache_validsg
2020-09-13 Luke Kenneth Casso... cache_valid_idx too large in dcache
2020-09-13 Luke Kenneth Casso... whoops, cache valid array too small in dcache
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... missing reservation address comparison
2020-09-12 Luke Kenneth Casso... dcache tidyup
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... add random dcache mem test
2020-09-12 Luke Kenneth Casso... cache valid corrupted: fixed
2020-09-12 Luke Kenneth Casso... adding names to array signals
2020-09-12 Luke Kenneth Casso... whoops, indentation error
2020-09-12 Luke Kenneth Casso... enable Display debugs
2020-09-12 Luke Kenneth Casso... set bytesel in dcache store
2020-09-11 Luke Kenneth Casso... separat stbs_done into ld/st
2020-09-11 Luke Kenneth Casso... dcache load/store test
2020-09-11 Luke Kenneth Casso... debugging dcache
2020-09-11 Luke Kenneth Casso... connect up WB SRAM to dcache test
2020-09-11 Luke Kenneth Casso... start on dcache test
2020-09-11 Luke Kenneth Casso... missing comb +=
2020-09-11 Luke Kenneth Casso... missing maybe_tlb_plrus
2020-09-11 Luke Kenneth Casso... WAY_BITS not TLB_WAY_BITS
2020-09-11 Luke Kenneth Casso... try to get better DTLBUpdate
2020-09-11 Luke Kenneth Casso... simplify dcache pending
2020-09-11 Luke Kenneth Casso... move dcache pending test to separate module
2020-09-11 Luke Kenneth Casso... more error correction in dcache
2020-09-11 Luke Kenneth Casso... use module for TLBUpdate
2020-09-11 Luke Kenneth Casso... add brackets round if & in dcache
2020-09-11 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-09-10 Luke Kenneth Casso... simplify read/write pte
2020-09-10 Luke Kenneth Casso... eek, big sort-out of syntax errors in dcache.py, now...
2020-09-10 Luke Kenneth Casso... starting on dcache syntax errors
2020-09-10 Luke Kenneth Casso... add PLRU microwatt conversion
2020-09-10 Luke Kenneth Casso... add function calls to construct dcache
2020-09-10 Luke Kenneth Casso... correct some errors introduced in dcache.py
2020-09-09 Luke Kenneth Casso... more laborious line-by-line checking of dcache.py conve...
2020-09-07 Luke Kenneth Casso... large stack of moving stuff around in dcache
2020-09-07 Luke Kenneth Casso... adjust indentation of dcache_slow
2020-09-07 Luke Kenneth Casso... more dcache translation
2020-09-07 Luke Kenneth Casso... more dcache translation
2020-09-03 Luke Kenneth Casso... do more on dcache conversion
2020-08-30 Luke Kenneth Casso... working on dcache.py
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza...
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb...
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu...
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
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