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Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git]
/
src
/
soc
/
experiment
/
lsmem.py
2021-08-24
Luke Kenneth Casso...
big rename, global/search/replace of ready_o with o_rea...
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2020-06-27
Luke Kenneth Casso...
fix TestMemLoadStoreUnit, it required a FSM to monitor...
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2020-06-26
Luke Kenneth Casso...
oops forgot to initialise base class of TestMemLoadStor...
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2020-06-26
Luke Kenneth Casso...
whitespace
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2020-06-26
Luke Kenneth Casso...
code-morph which redirects lsmem unit test through...
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2020-06-25
Luke Kenneth Casso...
add extra parameter, mask_wid, to TestMemLoadStoreUnit
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2020-06-25
Luke Kenneth Casso...
rename LoadStoreInterface signals to include _i and...
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2020-06-25
Luke Kenneth Casso...
whitespace
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2020-06-24
Michael Nolan
Have lsmem handle stall and valid signals correctly
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2020-06-24
Michael Nolan
Add handling of byte reads and writes
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2020-06-24
Michael Nolan
Add more complete testbench for lsmem.py
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2020-06-24
Michael Nolan
Super basic first try of testmem with load store unit...
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2020-06-24
Luke Kenneth Casso...
import minerva and use LoadStoreUnitInterface
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2020-06-24
Michael Nolan
Add specification for load store interface
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