Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src / soc / experiment / lsmem.py
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-26 Luke Kenneth Casso... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface